The PMP5364 reference design provides 5V at 20A (100W) from a standard 48V telecom input with up to 95% efficiency. This design uses the UCC2897A active clamp controller along with TI NexFET synchronous rectifiers. The low Rdson of the CSD17301Q5A reduces conduction losses and die area of the synchronous rectifiers. The circuit is built in an industry standard 1/4 brick footprint.
| Output voltage options | PMP5364.1 |
|---|---|
| Vin (Min) (V) | 36 |
| Vin (Max) (V) | 72 |
| Vout (Nom) (V) | 5 |
| Iout (Max) (A) | 20 |
| Output Power (W) | 100 |
| Isolated/Non-Isolated | Isolated |
| Input Type | DC |
| Topology | Forward- Active Clamp^Forward- Synchronous |
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| Test report | PMP5364 Test Results | Nov. 11, 2011 |
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