RS-485 interface with integrated 1.8-V level-shift capability


Design files


This circuit demonstrates the implementation of a low power, RS-485 transceiver with selectable data rate and flexible I/O logic levels. A dual-output LDO allows for operation with either 1.8V or 3.3V interface logic levels. A slew rate selection pin allows for driver slew rate control, enabling low-speed data transmission (250kbps) over long distances, or high-speed data transmission (20Mbps) over shorter bus lengths.

  • Interface with 1.8V or 3.3V logic levels
  • Selectable data rates: 250kbps or 20Mbps
  • Connect up to 256 nodes to the bus
  • IEC 61000-4-2 protection up to 16kV
  • IEC 61000-4-4 protection up to 4kV

A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU270.PDF (106 K)

Test results for the reference design, including efficiency graphs, test prerequisites and more

TIDR481.PDF (144 K)

Detailed schematic diagram for design layout and components

TIDR482.PDF (101 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDC338.ZIP (76 K)

Design file that contains information on physical board layer of design PCB


Includes TI products in the design and potential alternatives.

RS-485 & RS-422 transceivers

SN65HVD013.3-V RS-485 transceiver with 1.65-V I/O supply & selectable data rate

Data sheet document-pdfAcrobat PDF open-in-new HTML

Technical documentation

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Type Title Date
Test report TIDA-00193 Test Results Mar. 25, 2014

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