TIDEP0060

Optimized Radar System Reference Design Using a DSP+ARM SoC

TIDEP0060

Design files

Overview

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End (DFE) processing. Connecting to the ADC14X250 and DAC38J84 provides an efficient solution for avionics and defense applications such radar, electronic warfare, compute platforms and transponders.

Features
  • Easy integration of signal processor to data converters over JESD204B
  • Sampling of a single 100MHz channel, when connected to ADC14X250
  • DFE processing for filtering, down-sampling or up-sampling; FFTC hardware accelerator to offload compute-intensive 2D FFT operations, achieving low latency and high accuracy
  • Wideband sampling with JESD attached signal processing solution including Digital Signal Processor (DSP), ADC and DAC boards, demo software, configuration GUIs and Getting Started Guide
  • A robust demonstration and development platform including three EVMs, a deterministic latency card, schematic, BOM, user guide, benchmarks, software and demos
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUB89.PDF (2777 K)

Reference design overview and verified performance test data

TIDRKG3.PDF (1357 K)

Detailed schematic diagram for design layout and components

TIDRKG4.PDF (100 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRKG5.ZIP (2281 K)

Files used for 3D models or 2D drawings of IC components

TIDRKG6.ZIP (4391 K)

Files used for 3D models or 2D drawings of IC components

Products

Includes TI products in the design and potential alternatives.

Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Digital signal processors (DSPs)

66AK2L06Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Data sheet: PDF
High-speed ADCs (≥10 MSPS)

ADC14X25014-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
High-speed DACs (>10 MSPS)

DAC38J84Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)

Data sheet: PDF

Technical documentation

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Type Title Date
* White paper Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce Dec. 17, 2015
* Design guide Optimized Radar System Design Using a DSP+ARM SoC and ADC14X250 Design Guide Dec. 08, 2015
Application note 66AK2L06 JESD Attachment to ADC14X250/DAC38J84 (Rev. A) Jun. 24, 2016
Product overview 66AK2L06 SoC Product Bulletin Apr. 15, 2015

Related design resources

Software development

SOFTWARE DEVELOPMENT KIT (SDK)
BIOSLINUXMCSDK SYS/BIOS and Linux Multicore Software Development Kits (MCSDK) for C66x, C647x, C645x Processors PROCESSOR-SDK-K2L Processor SDK for 66AK2LX Processors - Linux and TI-RTOS support RFSDK Radio Frequency Software Developer Kit (RFSDK)

Support & training

TI E2E™ forums with technical support from TI engineers

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