TSW14J56EVM

Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps

TSW14J56EVM

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Overview

The Texas Instruments TSW14J56 Evaluation Module (EVM) is a next generation of pattern generator and data capture card used to evaluate performances of the new Texas Instruments (TI) JESD204B family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC).

Populated with an Arria V GZ device and using Altera’s JESD204B IP solution, the TSW14J56 can be dynamically configurable to support all lanes speeds from 600Mbps to 12.5Gbps, from 1 to 8 lanes, 1 to 16 converters, and 1 to 4 octets per frame.

Together with the accompanying High Speed Data Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVM’s and generates and sends desired test patterns to DAC EVM’s. 

  • Quickly evaluate JESD204B DAC and ADC performance using TI High Speed Data Converter Pro software
  • Direct connection to all TI JESD204B High Speed Data Converter EVM’s using an FMC standard connector
  • Quarter rate DDR3 controllers supporting up to 800MHz DDR3 operation
  • JESD RX and TX IP cores with 10 routed transceiver channels
  • Many available general purpose IO’s (status signals, SPI interface, etc.) between the FPGA and the FMC connector
  • SPI/JTAG reconfigurable JESD core parameters: L,M,K,F,HD,S etc.
  • Support for SUBCLASS 0 and 1 operation
  • Dynamically reconfigurable transceiver data rate using HSDC Pro software.
    • Operating range from 0.611Gbps to 12.5Gbps
  • An onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC and GUI
  • 32 Gb DDR3 SDRAM (total of 2G 16-bit samples).
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Evaluation board

TSW14J56EVM – Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps

Evaluation board

TSW14J56REVD_V3.03_FPGA_FIRMWARE – FPGA firmware for TSW14J56

Version: 3.03
Release date: 09/01/2015
GUI for evaluation module (EVM)

HSDC Pro GUI Software Release Notes (Rev. I) – SLAZ568I.PDF (349KB)

GUI for evaluation module (EVM)

HSDC Pro GUI Software Release Notes (Rev. J) – SLAZ568J.PDF (205KB)

GUI for evaluation module (EVM)

High Speed Data Converter Pro GUI Installer, v5.00 (Rev. U) – SLWC107U.ZIP (515773KB)

Support software

Software for Creating High Speed DAC Patterns (Win 7 Version) – SLWC110.ZIP (465178KB)

Support software

Software for Creating High Speed DAC Patterns (XP Version) – SLWC111.ZIP (448136KB)

Firmware

TSW14J56EVM FPGA Firmware – SLWC113.ZIP (21296KB)

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

TSW14J56EVM Design Package (Rev. D) SLRR014D.ZIP (14562 KB)

Technical documentation

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Type Title Date
* User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) Jan. 11, 2016
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
More literature TSW14J56EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
Application note Automated Data Transfer Between TSW40RF8x and TSW14J56 using MATLAB Aug. 02, 2017
User guide High-Speed Data Converter Pro GUI User's Guide (Rev. D) Mar. 16, 2017
More literature TSW14J56EVM FPGA Firmware Jan. 06, 2016
Application note Extending JESD204B Link Distance on Low-Cost Substrates Dec. 22, 2015
User guide Pipeline ADC Code Error Rate Analysis and Measurement Nov. 03, 2015
Technical articles JESD204B: Serial link quality tradeoffs and tools for optimization Mar. 20, 2015
Technical articles JESD204B: Determining your link configuration Sep. 24, 2014

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