SN65LVDS101EVM
SN65LVDS101 評估模組
SN65LVDS101EVM
概覽
The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to 50-ohm oscilloscope inputs. Single-ended LVPECL signals can also be applied by using the Vbb reference output voltage provided by either the SN65LVDS100/101 or SN65CML100.
特點
Hardware: SN65LVDS100/101EVM or SN65CML100EVM PWB
- Screw-type SMA jacks serve as the I/O connectors
- Banana jacks serve as the DC power input terminals
Literature:
a) The SN65LVDS100/101EVM or SN65CML100EVM user's guide (SLLU040A) Includes:
- schematic
- board layout
- test results
b) The SN65LVDS100/101 data sheet (SLLS516)
c) Or the SN65CML100 data sheet (SLLS547)
LVDS、M-LVDS 和 PECL IC
技術文件
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TI 所選的重要文件
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| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | EVM User's guide | 2-GBPS Differential Repeater EVM (Rev. A) | 2002/11/11 | |||
| 證書 | SN65LVDS101EVM EU Declaration of Conformity (DoC) | 2019/1/2 |