SN65MLVD2-3EVM
SN65MLVD2-3EVM 評估模組
SN65MLVD2-3EVM
概覽
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, the corresponding channel is enabled; when /RE = high, the corresponding channel is disabled.
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations withloss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.
The devices are characterized for operation from -40°C to 85°C.
特點
- Low-Voltage Differential 30Ω to 55Ω Line Data and Clock Receivers for Signaling Rates† up to Transmission via Backplanes and Cables 250 Mbps; Clock Frequencies up to 125 MHz
- SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
- SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
- Wide Receiver Input Common-Mode VoltageRange, -1 V to 3.4 V, Allows 2 V of Ground Noise
- Improved VIT (35 mV)
- Meets or Exceeds the M-LVDS StandardTIA/EIA-899 for Multipoint Topology
- High Input Impedance with Low SupplyVoltage
- Bus-Pin HBM ESD Protection Exceeds 9 kV
- Packaged in 8-Pin SON (DRB) 70% SmallerThan 8-Pin SOIC
† The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).
LVDS、M-LVDS 和 PECL IC
技術文件
| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | EVM User's guide | Mulitpoint-Low Voltage Differential Sgnaling (M-LVDS) EVM | 2007/6/29 | |||
| 證書 | SN65MLVD2-3EVM EU Declaration of Conformity (DoC) | 2019/1/2 |