SCES424M
January 2003 – August 2022
SN74LVC1G3157
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Analog Switch Characteristics
6.7
Switching Characteristics 85°C
6.8
Switching Characteristics 125°C
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRY|6
MPDS221F
DSF|6
MPDS301G
YZP|6
MXBG347
DTB|6
MPSS095B
DCK|6
MPDS114E
DRL|6
MPDS159H
DBV|6
MPDS026Q
Thermal pad, mechanical data (Package|Pins)
DRY|6
QFND138E
Orderable Information
sces424m_oa
sces424m_pm
1
Features
ESD protection exceeds JESD 22
2000-V Human Body Model (A114-A)
1000-V Charged-Device Model (C101)
1.65-V to 5.5-V V
CC
operation
Qualified for 125°C operation
Specified break-before-make switching
Rail-to-rail signal handling
Operating frequency typically 340 MHz at room temperature
High speed, typically 0.5 ns
(V
CC
= 3 V, C
L
= 50 pF)
Low ON-state resistance, typically ≉6 Ω
(V
CC
= 4.5 V)
Latch-up performance exceeds 100 mA Per JESD 78, class II