SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZMX|196
  • NWE|196
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11= 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA±, fIN = 347 MHz, AIN = –1 dBFS,fCLK = maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating temperature range provided in the Recommended Operating Conditions table
PARAMETERTEST CONDITIONSSUBGROUP(1)MINTYPMAXUNIT
FPBWFull-power input bandwidth
(–3 dB)(2)		Foreground calibration7.1GHz
Background calibration7.1
CERCode error rateDoes not include SerDes bit-error rate (BER)10–18Errors / Sample
NOISEDCDC input noise standard deviationNo input, foreground calibration, excludes DC offset, includes fixed interleaving spurs (fS / 2 and fS / 4 spurs)2.8LSB
NSDNoise spectral density, no input signal, excludes fixed interleaving spurs (fS / 2 and fS / 4 spur)Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration–152.4dBFS/Hz
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration–150.0
NFNoise figure, no input, ZS = 100 ΩMaximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration20.6dB
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration23.1
SNRSignal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spursfIN = 347 MHz, AIN = –1 dBFS55.8dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration57.1
fIN = 997 MHz, AIN = –1 dBFS55.5
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]51.054.9
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration56.1
fIN = 4997 MHz, AIN = –1 dBFS53.1
fIN = 6397 MHz, AIN = –1 dBFS51.9
fIN = 8197 MHz, AIN = –1 dBFS50.6
SNRSignal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spursfIN = 347 MHz, AIN = –16 dBFS56.5dBFS
fIN = 997 MHz, AIN = –16 dBFS56.6
fIN = 2482 MHz, AIN = –16 dBFS56.5
fIN = 4997 MHz, AIN = –16 dBFS56.5
fIN = 6397 MHz, AIN = –16 dBFS56.5
fIN = 8197 MHz, AIN = –16 dBFS56.2
SINADSignal-to-noise and distortion ratio, large signal, excluding DC and fS / 2 fixed spursfIN = 347 MHz, AIN = –1 dBFS54.6dBFS
fIN = 997 MHz, AIN = –1 dBFS53.6
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]43.951.3
fIN = 4997 MHz, AIN = –1 dBFS50.8
fIN = 6397 MHz, AIN = –1 dBFS49.6
fIN = 8197 MHz, AIN = –1 dBFS47.2
ENOBEffective number of bits, large signal, excluding DC and fS / 2 fixed spursfIN = 347 MHz, AIN = –1 dBFS8.8Bits
fIN = 997 MHz, AIN = –1 dBFS8.6
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]7.08.2
fIN = 4997 MHz, AIN = –1 dBFS8.1
fIN = 6397 MHz, AIN = –1 dBFS7.9
fIN = 8197 MHz, AIN = –1 dBFS7.5
SFDRSpurious-free dynamic range, large signal, excluding DC, fS / 4 and fS / 2 fixed spursfIN = 347 MHz, AIN = –1 dBFS66dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration67
fIN = 997 MHz, AIN = –1 dBFS60
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]4556
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration52
fIN = 4997 MHz, AIN = –1 dBFS58
fIN = 6397 MHz, AIN = –1 dBFS57
fIN = 8197 MHz, AIN = –1 dBFS52
SFDRSpurious-free dynamic range, small signal, excluding DC, fS / 4 and fS / 2 fixed spursfIN = 347 MHz, AIN = –16 dBFS70dBFS
fIN = 997 MHz, AIN = –16 dBFS66
fIN = 2482 MHz, AIN = –16 dBFS66
fIN = 4997 MHz, AIN = –16 dBFS67
fIN = 6397 MHz, AIN = –16 dBFS68
fIN = 8197 MHz, AIN = –16 dBFS65
fS / 2fS / 2 fixed interleaving spur, independent of input signalNo input, OS_CAL disabled, spur can be improved by running OS_CAL–64dBFS
fS / 4fS / 4 fixed interleaving spur, independent of input signalNo input[4, 5, 6]–70–50dBFS
HD22nd-order harmonic distortionfIN = 347 MHz, AIN = –1 dBFS–72dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–69
fIN = 997 MHz, AIN = –1 dBFS–70
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]–71–58
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–73
fIN = 4997 MHz, AIN = –1 dBFS–66
fIN = 6397 MHz, AIN = –1 dBFS–65
fIN = 8197 MHz, AIN = –1 dBFS–67
HD33rd-order harmonic distortionfIN = 347 MHz, AIN = –1 dBFS–71dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–67
fIN = 997 MHz, AIN = –1 dBFS–70
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]–67–58
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration–62
fIN = 4997 MHz, AIN = –1 dBFS–61
fIN = 6397 MHz, AIN = –1 dBFS–59
fIN = 8197 MHz, AIN = –1 dBFS–56
fS / 2-fINfS / 2 – fIN interleaving spur, signal dependentfIN = 347 MHz, AIN = –1 dBFS–68dBFS
fIN = 997 MHz, AIN = –1 dBFS–63
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]–56–45
fIN = 4997 MHz, AIN = –1 dBFS–58
fIN = 6397 MHz, AIN = –1 dBFS–57
fIN = 8197 MHz, AIN = –1 dBFS–56
fS / 4±fINfS / 4 ± fIN interleaving spurs, signal dependentfIN = 347 MHz, AIN = –1 dBFS–76dBFS
fIN = 997 MHz, AIN = –1 dBFS–74
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]–75–58
fIN = 4997 MHz, AIN = –1 dBFS–73
fIN = 6397 MHz, AIN = –1 dBFS–69
fIN = 8197 MHz, AIN = –1 dBFS–70
SPURWorst harmonic 4th-order distortion or higherfIN = 347 MHz, AIN = –1 dBFS–74dBFS
fIN = 997 MHz, AIN = –1 dBFS–75
fIN = 2482 MHz, AIN = –1 dBFS[4, 5, 6]–74–60
fIN = 4997 MHz, AIN = –1 dBFS–70
fIN = 6397 MHz, AIN = –1 dBFS–70
fIN = 8197 MHz, AIN = –1 dBFS–66
IMD33rd-order intermodulation distortionfIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–89dBFS
fIN = 997 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–79
fIN = 2482 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–73
fIN = 4997 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–65
fIN = 6397 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–61
fIN = 8197 MHz ± 5 MHz,
AIN = –7 dBFS per tone		–54
(1) For subgroup definitions, please see Table 6-1.
(2) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth.