SBAS653B April   2014  – October 2020 ADS4245-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics: LVDS And CMOS Modes
    9. 6.9  Typical Characteristics:
    10. 6.10 Typical Characteristics: General
    11. 6.11 Typical Characteristics: Contour
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
      2. 7.4.2 Gain For SFDR/SNR Trade-Off
      3. 7.4.3 Offset Correction
      4. 7.4.4 Power-Down
        1. 7.4.4.1 Global Power-Down
        2. 7.4.4.2 Channel Standby
        3. 7.4.4.3 Input Clock Stop
      5. 7.4.5 Digital Output Information
        1. 7.4.5.1 Output Interface
        2. 7.4.5.2 DDR LVDS Outputs
        3. 7.4.5.3 LVDS Buffer
        4. 7.4.5.4 Parallel CMOS Interface
        5. 7.4.5.5 CMOS Interface Power Dissipation
        6. 7.4.5.6 Multiplexed Mode Of Operation
        7. 7.4.5.7 Output Data Format
      6. 7.4.6 Device Configuration
        1. 7.4.6.1 Parallel Configuration Only
        2. 7.4.6.2 Serial Interface Configuration Only
        3. 7.4.6.3 Using Both Serial Interface And Parallel Controls
        4. 7.4.6.4 Parallel Configuration Details
        5. 7.4.6.5 Serial Interface Details
          1. 7.4.6.5.1 Register Initialization
          2. 7.4.6.5.2 Serial Register Readout
    5. 7.5 Serial Register Map
    6. 7.6 Description Of Serial Registers
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Clock Input
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Input
        1. 8.2.1.1 Design Requirements for Drive Circuits
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding
      2. 10.1.2 Supply Decoupling
      3. 10.1.3 Exposed Pad
      4. 10.1.4 Routing Analog Inputs
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Support
        1. 11.1.1.1 Definition Of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Description Of Serial Registers

76543210
000000RESETREADOUT
Bits[7:2] Always write '0'
Bit 1 RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0 READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT terminal is placed in high-impedance state.
1 = Serial readout enabled; the SDOUT terminal functions as a serial data readout with CMOS logic levels running from the DRVDD supply. See the Serial Register Readout section.
76543210
LVDS SWING00
Bits[7:2] LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming swing.
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing decreases to ±200mV
001111 = LVDS swing decreases to ±125mV
Bits[1:0] Always write '0'
76543210
000000HIGH PERF MODE
Bits[7:2] Always write '0'
Bits[1:0] HIGH PERF MODE: High-performance mode
00 = Default performance
01 = Do not use
10 = Do not use
11 = Obtain best performance across sample clock and input signal frequencies
76543210
CH A GAIN0CH A TEST PATTERNS
Bits[7:4] CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5dB steps for channel A.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Bit 3 Always write '0'
Bits[2:0] CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
Output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
Output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
76543210
000DATA FORMAT000
Bits[7:5] Always write '0'
Bits[4:3] DATA FORMAT: Data format selection
00 = Twos complement
01 = Twos complement
10 = Twos complement
11 = Offset binary
Bits[2:0] Always write '0'
76543210
CH B GAIN0CH B TEST PATTERNS
Bits[7:4] CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5dB steps for channel B.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Bit 3 Always write '0'
Bits[2:0] CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
Output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
Output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
76543210
00ENABLE OFFSET CORR00000
Bits[7:6] Always write '0'
Bit 5 ENABLE OFFSET CORR: Offset correction setting
This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0] Always write '0'
76543210
00CUSTOM PATTERN D13CUSTOM PATTERN D12CUSTOM PATTERN D11CUSTOM PATTERN D10CUSTOM PATTERN D9CUSTOM PATTERN D8
Bits[7:6] Always write '0'
Bits[5:0] CUSTOM PATTERN D[13:8]
These are the six upper bits of the custom pattern available at the output instead of ADC data.
76543210
Bits[7:0]CUSTOM PATTERN D[7:0]
These are the eight upper bits of the custom pattern available at the output instead of ADC data.
76543210
LVDS CMOSCMOS CLKOUT STRENGTH00DIS OBUF
Bits[7:6] LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4] CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits[3:2] Always write '0'
Bits[1:0] DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output interface. When powered down, the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
76543210
CLKOUT FALL POSNCLKOUT RISE POSNEN DIGITAL000
Bits[7:6] CLKOUT FALL POSN
In LVDS mode:
00 = Default
01 = The falling edge of the output clock advances by 450 ps
10 = The falling edge of the output clock advances by 150 ps
11 = The falling edge of the output clock is delayed by 550 ps
In CMOS mode:
00 = Default
01 = The falling edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The falling edge of the output clock advances by 100 ps
Bits[5:6] CLKOUT RISE POSN
In LVDS mode:
00 = Default
01 = The rising edge of the output clock advances by 450 ps
10 = The rising edge of the output clock advances by 150 ps
11 = The rising edge of the output clock is delayed by 250 ps
In CMOS mode:
00 = Default
01 = The rising edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The rising edge of the output clock advances by 100 ps
Bit 3 EN DIGITAL: Digital function enable
0 = All digital functions disabled
1 = All digital functions (such as test patterns, gain, and offset correction) enabled
Bits[2:0] Always write '0'
76543210
STBYLVDS CLKOUT STRENGTHLVDS DATA STRENGTH00PDN GLOBAL00
Bit 7 STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50µs).
Bit 6 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50Ω external termination
Bit 5 LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100Ω external termination
1 = All LVDS data buffers have double strength to be used with 50Ω external termination
Bits[4:3] Always write '0'
Bit 2 PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered down. Wakeup time from this mode is slow (typically 100µs).
Bits[1:0] Always write '0'
76543210
0000000HIGH FREQ MODE CH B
Bits[7:1] Always write '0'
Bit 0 HIGH FREQ MODE CH B: High-frequency mode for channel B
0 = Default
1 = Use this mode for high input frequencies
76543210
0000000HIGH FREQ MODE CH A
Bits[7:1] Always write '0'
Bit 0 HIGH FREQ MODE CH A: High-frequency mode for channel A
0 = Default
1 = Use this mode for high input frequencies
76543210
CH A OFFSET PEDESTAL00
Bits[7:2] CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A pedestal can be added to the final converged value by programming these bits. See the Offset Correction section. Channels can be independently programmed for different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+32 by adding pedestal D7-D2.
ADS4245 (Program Bits D[7:2])
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
111101 = Midcode-3
…
100000 = Midcode-32
Bits[1:0] Always write '0'
76543210
CH B OFFSET PEDESTAL00
Bits[7:2] CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A pedestal can be added to the final converged value by programming these bits; see the Offset Correction section. Channels can be independently programmed for different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+32 by adding pedestal D[7:2].
ADS424x (Program Bits D[7:2])
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
111101 = Midcode-3
…
100000 = Midcode-32
Bits[1:0] Always write '0'
76543210
FREEZE OFFSET CORR0OFFSET CORR TIME CONSTANT00
Bit 7 FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen, the last estimated value is used for offset correction of every clock cycle. See the Offset Correction section.
Bit 6 Always write '0'
Bits[5:2] OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction section.
Bits[1:0] Always write '0'
76543210
0000000LOW SPEED MODE CH B
Bits[7:1] Always write '0'
Bit 0 LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1' before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
76543210
000EN LOW SPEED MODE0000
Bits[7:5] Always write '0'
Bit 4 EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits (ADS42x5 and ADS42x6 only)
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW SPEED MODE CH A register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits[3:0] Always write '0'
76543210
000000EN LVDS SWING
Bits[7:2] Always write '0'
Bits[1:0] EN LVDS SWING: LVDS swing enable
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
76543210
0000LOW SPEED MODE CH A000
Bits[7:4] Always write '0'
Bit 3 LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1' before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits[2:0] Always write '0'