SBAS603B Data sheet

SBAS603B April 2013 – November 2020 ADS4449

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

ZCR|144
- MPBGA77A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9.2.7 Clock Input

The device clock inputs can be driven differentially with a sine, LVPECL, or LVDS source with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors, as shown in Figure 9-10. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL, LVDS, and LVCMOS clock sources (see Figure 9-11, Figure 9-12, and Figure 9-13).

For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 V_PP to obtain best performance. A clock source with very low jitter is recommended for high input frequency sampling. Band-pass filtering of the clock source can help reduce the effects of jitter. With a non-50% duty cycle clock input, performance does not change.

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 9-10 Internal Clock Buffer

R_T is the termination resistor (optional).

Figure 9-11 Differential Sine-Wave Clock Driving Circuit

Figure 9-12 LVPECL Clock Driving Circuit

Figure 9-13 LVDS Clock Driving Circuit

Figure 9-14 Typical LVCMOS Clock Driving Circuit