SBAS682D November   2014  – December 2015 ADS7044

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Analog Input
      3. 8.3.3 ADC Transfer Function
      4. 8.3.4 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration
        1. 8.4.1.1 Offset Calibration on Power-Up
        2. 8.4.1.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply DAQ with the ADS7044
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Antialiasing Filter
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Ultra-Low Power and Ultra-Small, High CMRR DAQ Circuit with the ADS7044
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power-Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Estimating Digital Power Consumption
    3. 10.3 Optimizing Power Consumed by the Device
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCU|8
  • RUG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power-Supply Recommendations

10.1 AVDD and DVDD Supply Recommendations

The device has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible ranges. The AVDD supply also defines the full-scale input range of the device. Decouple the AVDD and DVDD pins individually with 1-µF ceramic decoupling capacitors, as shown in Figure 45. The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both supplies are powered from the same source, a minimum capacitor value of 220 nF is required for decoupling.

ADS7044 ai_supply_bas608.gif Figure 45. Power-Supply Decoupling

10.2 Estimating Digital Power Consumption

The current consumption from the DVDD supply depends on the DVDD voltage, load capacitance on the SDO line, and the output code. The load capacitance on the SDO line is charged by the current from the SDO pin on every rising edge of the data output and is discharged on every falling edge of the data output. The current consumed by the device from the DVDD supply can be calculated by Equation 4:

Equation 4. IDVDD = C × V × f

where

  • C = Load capacitance on the SDO line,
  • V = DVDD supply voltage, and
  • f = Number of transitions on the SDO output.

The number of transitions on the SDO output depends on the output code, and thus changes with the analog input. The maximum value of f occurs when data output on the SDO change on every SCLK. SDO changing on every SCLK results in an output code of AAAh or 555h. For an output code of AAAh or 555h at a 1-MSPS throughput, the frequency of transitions on the SDO output is 6 MHz.

To keep the current consumption at the lowest possible value, the DVDD supply must be kept at the lowest permissible value and the capacitance on the SDO line must be kept as low as possible.

10.3 Optimizing Power Consumed by the Device

  • Keep the analog supply voltage (AVDD) as per the analog input full-scale range (FSR) requirement.
  • Keep the digital supply voltage (DVDD) at the lowest permissible value.
  • Reduce the load capacitance on the SDO output.
  • Run the device at optimum throughput. Power consumption reduces with throughput.