SLAS600C May   2008  – December 2016 ADS8319

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: +VBD ≥ 4.5 V
    7. 7.7 Timing Requirements: 4.5 V > +VBD ≥ 2.375 V
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Driver Amplifier Choice
      3. 8.3.3 Driver Amplifier Configurations
      4. 8.3.4 Reference
      5. 8.3.5 Power Saving
      6. 8.3.6 Digital Output
      7. 8.3.7 SCLK Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 CS Mode
        1. 8.4.1.1 3-Wire CS Mode Without Busy Indicator
        2. 8.4.1.2 3-Wire CS Mode With Busy Indicator
        3. 8.4.1.3 4-Wire CS Mode Without Busy Indicator
        4. 8.4.1.4 4-Wire CS Mode With Busy Indicator
      2. 8.4.2 Daisy-Chain Mode
        1. 8.4.2.1 Daisy-Chain Mode Without Busy Indicator
        2. 8.4.2.2 Daisy-Chain Mode With Busy Indicator
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
+IN pin voltage –0.3 +VA + 0.3 V
+IN pin current ±130 mA
–IN pin voltage –0.3 0.3 V
–IN pin current ±130 mA
+VA to AGND –0.3 7 V
+VBD to BDGND –0.3 7 V
Digital input voltage to GND –0.3 +VBD + 0.3 V
Digital output to GND –0.3 +VBD + 0.3 V
Maximum VSSOP reflow temperature(2) 260 °C
Maximum VSON reflow temperature(2) 260 °C
Operating free-air temperature, TA –40 85 °C
Junction temperature, TJ(MAX) 150 °C
Storage temperature, Tstg –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The device is rated to MSL2 260°C, as per the JSTD-020 specification.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
+VA Analog power-supply voltage 4.5 5 5.5 V
+VBD Digital I/O-supply voltage 2.375 3.3 5.5 V
VREF Reference voltage 2.25 4.096 +VA + 0.1 V
TA Operating temperature –40 85 °C

Thermal Information

THERMAL METRIC(1) ADS8319 UNIT
DGS (VSSOP) DRC (VSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 107.5 87.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 21.8 31.1 °C/W
RθJB Junction-to-board thermal resistance 24.2 25.5 °C/W
ψJT Junction-to-top characterization parameter 0.6 1 °C/W
ψJB Junction-to-board characterization parameter 24.4 29.2 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, VREF = 4 V, and fSAMPLE = 500 kHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1) +IN – (–IN) 0 VREF V
Operating input +IN –0.1 VREF + 0.1 V
–IN –0.1 0.1
Input capacitance 59 pF
Input leakage current During acquisition 1000 pA
SYSTEM PERFORMANCE
Resolution 16 Bits
No missing codes 16 Bits
INL Integral linearity(6) ADS8319I –2.5 ±1.2 2.5 LSB(2)
ADS8319IB –1.5 ±1 1.5
DNL Differential linearity At 16-bit level ADS8319I –1 ±0.65 1.5 LSB
ADS8319IB –1 ±0.5 1
EO Offset error(3) –1.5 ±0.3 1.5 mV
EG Gain error –0.03 ±0.0045 0.03 %FSR
CMRR Common-mode rejection ratio With common-mode input
signal = 200 mVPP at 500 kHz
78 dB
PSRR Power-supply rejection ratio At FFF0h output code 80 dB
Transition noise 0.5 LSB
SAMPLING DYNAMICS
tCONV Conversion time +VBD = 5 V 1400 ns
+VBD = 3 V 1400
Acquisition time +VBD = 5 V 600 ns
+VBD = 3 V 600
Maximum throughput rate with or without latency 0.5 MHz
Aperture delay 2.5 ns
Aperture jitter, RMS 6 ps
Step response Settling to 16-bit accuracy 600 ns
Overvoltage recovery Settling to 16-bit accuracy 600 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion(4) VIN 0.4 dB below FS at 1 kHz, VREF = 5 V –111 dB
VIN 0.4 dB below FS at 10 kHz, VREF = 5 V –106
VIN 0.4 dB below FS at 100 kHz, VREF = 5 V –89
SNR Signal-to-noise ratio ADS8319IB, VIN 0.4 dB below FS at 1 kHz,
VREF = 5 V
92 dB
VIN 0.4 dB below FS at 1 kHz, VREF = 5 V 93.9
VIN 0.4 dB below FS at 10 kHz, VREF = 5 V 93.6
VIN 0.4 dB below FS at 100 kHz, VREF = 5 V 92.2
SINAD Signal-to-noise + distortion VIN 0.4 dB below FS at 1 kHz, VREF = 5 V 93.8 dB
VIN 0.4 dB below FS at 10 kHz, VREF = 5 V 93.4
VIN 0.4 dB below FS at 100 kHz, VREF = 5 V 87.4
SFDR Spurious-free dynamic range VIN 0.4 dB below FS at 1 kHz, VREF = 5 V 113 dB
VIN 0.4 dB below FS at 10 kHz, VREF = 5 V 107
VIN 0.4 dB below FS at 100 kHz, VREF = 5 V 90
–3-dB small-signal bandwidth 15 MHz
EXTERNAL REFERENCE INPUT
VREF Reference input 2.25 4.096 +VA + 0.1 V
Reference input current(5) During conversion 250 µA
POWER SUPPLY REQUIREMENTS
Power-supply voltage +VBD 2.375 3.3 5.5 V
+VA 4.5 5 5.5
Supply current +VA, 500-kHz sample rate 3.6 4.5 mA
PVA Power dissipation +VA = 5 V, 500-kHz sample rate 18 22.5 mW
IVApd Device power-down current(7) +VA = 5 V 50 300 nA
LOGIC FAMILY CMOS
VIH Input HIGH logic level IIH = 5 µA +(0.7 × VBD) +VBD + 0.3 V
VIL Input LOW logic level IIL = 5 µA –0.3 +(0.3 × VBD)
VOH Output HIGH logic level IOH = 2 TTL loads +VBD – 0.3 +VBD
VOL Output LOW logic level IOL = 2 TTL loads 0 0.4
Ideal input span, does not include gain or offset error.
LSB means least significant bit.
Measured relative to actual measured reference.
Calculated on the first nine harmonics of the input frequency.
Can vary by ±20%.
This parameter is endpoint INL, not best fit.
The device automatically enters a power-down state at the end of every conversion and remains in a power-down state during the acquisition phase.

Timing Requirements: +VBD ≥ 4.5 V

All specifications are typical at –40°C to 85°C, +VA = 5 V, and +VBD ≥ 4.5 V, unless otherwise noted.
REFERENCE FIGURE MIN MAX UNIT
SAMPLING AND CONVERSION RELATED
tACQ Acquisition time Figure 50, Figure 52, Figure 53, Figure 55 600 ns
tcnv Conversion time 1400 ns
tcyc Time between conversions 2000 ns
t1 Pulse duration, CONVST high Figure 50, Figure 52 10 ns
t6 Pulse duration, CONVST low Figure 53, Figure 55, Figure 58 20 ns
I/O RELATED
tclk SCLK period Figure 50, Figure 52, Figure 53, Figure 55, Figure 58, Figure 60 20 ns
tclkl SCLK low time 9 ns
tclkh SCLK high time 9 ns
t2 SCLK falling edge to data remains valid 5 ns
t3 SCLK falling edge to next data valid delay 16 ns
ten Enable time, CONVST or SDI low to MSB valid Figure 50, Figure 53 15 ns
tdis Disable time, CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) Figure 50, Figure 52, Figure 53, Figure 55 12 ns
t4 Setup time, SDI valid to CONVST rising edge Figure 53, Figure 55 5 ns
t5 Hold time, SDI valid from CONVST rising edge 5 ns
t7 Setup time, SCLK valid to CONVST rising edge Figure 58 5 ns
t8 Hold time, SCLK valid from CONVST rising edge 5 ns

Timing Requirements: 4.5 V > +VBD ≥ 2.375 V

All specifications are typical at –40°C to 85°C, +VA = 5 V, and +4.5 V > +VBD ≥ 2.375 V, unless otherwise noted.
REFERENCE FIGURE MIN MAX UNIT
SAMPLING AND CONVERSION RELATED
tACQ Acquisition time Figure 50, Figure 52, Figure 53, Figure 55 600 ns
tcnv Conversion time 1400 ns
tcyc Time between conversions 2000 ns
t1 Pulse width CONVST high Figure 50, Figure 52 10 ns
t6 Pulse width CONVST low Figure 53, Figure 55, Figure 58 20 ns
I/O RELATED
tclk SCLK period Figure 50, Figure 52, Figure 53, Figure 55, Figure 58, Figure 60 30 ns
tclkl SCLK low time 13 ns
tclkh SCLK high time 13 ns
t2 SCLK falling edge to data remains valid 5 ns
t3 SCLK falling edge to next data valid delay 24 ns
ten CONVST or SDI low to MSB valid Figure 50, Figure 53 22 ns
tdis CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) Figure 50, Figure 52, Figure 53, Figure 55 15 ns
t4 SDI valid setup time to CONVST rising edge Figure 53, Figure 55 5 ns
t5 SDI valid hold time from CONVST rising edge 5 ns
t7 SCLK valid setup time to CONVST rising edge Figure 58 5 ns
t8 SCLK valid hold time from CONVST rising edge 5 ns
ADS8319 ld_cir_las568.gif Figure 1. Load Circuit for Digital Interface Timing
ADS8319 tm_vol_lvl_las568.gif Figure 2. Voltage Levels for Timing

Typical Characteristics

ADS8319 offset_sv_las600.gif Figure 3. Offset Error vs Supply Voltage
ADS8319 oe_vref_las600.gif Figure 5. Offset Error vs Reference Voltage
ADS8319 oe_ta_las600.gif Figure 7. Offset Error vs Free-Air Temperature
ADS8319 ge_histo_las600.gif Figure 9. Gain Error Drift Histogram
ADS8319 dnl_va_las600.gif Figure 11. Differential Nonlinearity vs Supply Voltage
ADS8319 dnl_vref_las600.gif Figure 13. Differential Nonlinearity vs Reference Voltage
ADS8319 dnl_ta_las600.gif Figure 15. Differential Nonlinearity vs Free-Air Temperature
ADS8319 enob_va_las600.gif Figure 17. Effective Number of Bits vs Supply Voltage
ADS8319 enob_ta_las600.gif Figure 19. Effective Number of Bits vs Free-Air Temperature
ADS8319 sinad_va_las600.gif Figure 21. Signal-to-Noise + Distortion vs Supply Voltage
ADS8319 thd_va_las600.gif Figure 23. Total Harmonic Distortion vs Supply Voltage
ADS8319 sinad_vref_las600.gif Figure 25. Signal-to-Noise + Distortion vs Reference Voltage
ADS8319 thd_vref_las600.gif Figure 27. Total Harmonic Distortion vs Reference Voltage
ADS8319 sinad_ta_las600.gif Figure 29. Signal-to-Noise + Distortion
vs Free-Air Temperature
ADS8319 thd_ta_las600.gif Figure 31. Total Harmonic Distortion
vs Free-Air Temperature
ADS8319 thd2_fi_las600.gif Figure 33. Total Harmonic Distortion
vs Signal Input Frequency
ADS8319 thd_sr_las600.gif Figure 35. Total Harmonic Distortion vs Source Resistance
ADS8319 icc_ta_las600.gif Figure 37. Supply Current vs Free-Air Temperature
ADS8319 pd_fs_las600.gif Figure 39. Power Dissipation vs Sampling Frequency
ADS8319 pwr_dwn_ta_las600.gif Figure 41. Power-Down Current vs Free-Air Temperature
ADS8319 inl_code_las600.gif Figure 43. INL
ADS8319 ge_sv_las600.gif Figure 4. Gain Error vs Supply Voltage
ADS8319 ge_vref_las600.gif Figure 6. Gain Error vs Reference Voltage
ADS8319 oe2_ta_las600.gif Figure 8. Gain Error vs Free-Air Temperature
ADS8319 ge_histo2_las600.gif Figure 10. Offset Error Drift Histogram
ADS8319 inl_va_las600.gif Figure 12. Integral Nonlinearity vs Supply Voltage
ADS8319 inl_vref_las600.gif Figure 14. Integral Nonlinearity vs Reference Voltage
ADS8319 inl_ta_las600.gif Figure 16. Integral Nonlinearity vs Free-Air Temperature
ADS8319 enob_vref_las600.gif Figure 18. Effective Number of Bits vs Reference Voltage
ADS8319 sfdr_va_las600.gif Figure 20. Spurious-Free Dynamic Range vs Supply Voltage
ADS8319 snr_va_las600.gif Figure 22. Signal-to-Noise Ratio vs Supply Voltage
ADS8319 sfdr_vref_las600.gif Figure 24. Spurious-Free Dynamic Range
vs Reference Voltage
ADS8319 snr_vref_las600.gif Figure 26. Signal-to-Noise Ratio vs Reference Voltage
ADS8319 sfdr_ta_las600.gif Figure 28. Spurious-Free Dynamic Range
vs Free-Air Temperature
ADS8319 snr_ta_las600.gif Figure 30. Signal-to-Noise Ratio vs Free-Air Temperature
ADS8319 sinad2_fi_las600.gif Figure 32. Signal-to-Noise + Distortion
vs Signal Input Frequency
ADS8319 histo_las600.gif Figure 34. DC Histogram of ADC Close to Center Code
ADS8319 icc_va_las600.gif Figure 36. Supply Current vs Supply Voltage
ADS8319 icc_fs_las600.gif Figure 38. Supply Current vs Sampling Frequency
ADS8319 pwr_dwn_va_las600.gif Figure 40. Power-Down Current vs Supply Voltage
ADS8319 dnl_code_las600.gif
Figure 42. DNL
ADS8319 ampli_f_las600.gif Figure 44. FFT