SBAS363E December   2009  – August 2016 ADS8331 , ADS8332

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Products
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: VA = 2.7 V
    6. 8.6  Electrical Characteristics: VA = 5 V
    7. 8.7  Timing Requirements: VA = 2.7 V
    8. 8.8  Timing Characteristics: VA = 5 V
    9. 8.9  Typical Characteristics: DC Performance
    10. 8.10 Typical Characteristics: AC Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Signal Conditioning
      2. 9.3.2 Analog Input
        1. 9.3.2.1 Driver Amplifier Choice
        2. 9.3.2.2 Bipolar to Unipolar Driver
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reference
      2. 9.4.2 Converter Operation
        1. 9.4.2.1 Manual Channel Select Mode
        2. 9.4.2.2 Auto Channel Select Mode
        3. 9.4.2.3 Start of a Conversion
        4. 9.4.2.4 Status Output Pin (EOC/INT)
        5. 9.4.2.5 Power-Down Modes and Acquisition Time
    5. 9.5 Programming
      1. 9.5.1 Digital Interface
        1. 9.5.1.1 Internal Register
      2. 9.5.2 Writing to the Converter
        1. 9.5.2.1 Configuring the Converter and Default Mode
      3. 9.5.3 Reading the Configuration Register
      4. 9.5.4 Reading the Conversion Result
        1. 9.5.4.1 TAG Mode
        2. 9.5.4.2 Daisy-Chain Mode
      5. 9.5.5 Reset Function
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
        1. 10.1.1.1 Reference Driver Circuit for VREF = 4.096 V
        2. 10.1.1.2 Reference Driver Circuit for VREF=2.5 V, VA=2.7 V
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 ADC Input RC Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for Low Noise and Distortion Performance for a 10-kHz Input Signal at 500 kSPS
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Ultra Low-Power DAQ Circuit for DC Input Signals at 10 kSPS per Channel
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

Figure 56 shows a board layout example for the ADS833x with the VQFN package. Use a ground plane underneath the device and partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference input signals away from noise sources. As shown in Figure 56, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the device.

The power sources to the device must be clean and well-bypassed. Use 10 μF, ceramic bypass capacitors in close proximity to the analog (VA) and digital (VBD) power-supply pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low impedance paths.

The REF+ reference input is bypassed with a 22 μF, X7S-grade, 0805-size, 10-V rated ceramic capacitors. Place the reference bypass capacitor as close as possible to the reference REF+ and REF- pins and connect the bypass capacitor using short, low-inductance connections. Avoid placing vias between the REF+ and REF- pins and the bypass capacitor. If the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation. A small 0.2-Ω to 0.5-Ω resistors (RREF) is used in series with the reference bypass capacitor to improve stability.

The fly-wheel RC filters are placed immediately next to the input pins. For applications measuring AC signals, COG (NPO) ceramic capacitors provide the best capacitance precision. Figure 56 shows input filter capacitors placed in close proximity to the INx analog input pins of the device.

12.2 Layout Example

ADS8331 ADS8332 apps_layout_sbas363.gif Figure 56. Layout Example for ADS833x