The host controller operates the device at the desired throughput by interleaving the conversion cycles and the data transfer frames.
The cycle time of the device, tcycle, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, tresp, is the time difference between the host controller initiating conversion C, and the host controller receiving the complete result for conversion C.
Figure 44 shows three conversion cycles: C, C + 1, and C + 2. Conversion C is initiated by a CONVST rising edge at time t = 0, and the conversion result becomes available for data transfer at tconv. However, this result is loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of conversion C + 1 (that is, before tcycle + tconv).
To achieve the rated performance specifications, the host controller must make sure that no digital signals toggle during the quiet acquisition time (tqt_acq) and quiet aperture time (td_cnvcap). Any noise during td_cnvcap may negatively affect the result of the ongoing conversion, whereas any noise during tqt_acq may negatively affect the result of the subsequent conversion.
This architecture allows for two distinct time zones (zone 1 and zone 2) to transfer data for each conversion. Zone 1 and zone 2 for conversion C are defined in Table 3.
|ZONE||STARTING TIME||ENDING TIME|
|Zone 1 for conversion C|
|Zone 2 for conversion C|
The response time includes the conversion time and the data transfer time, and thus is a function of the selected data transfer zone.
To achieve cycle time tcycle, the read time in zone 1 is given by Equation 5:
Then, the zone 1 data transfer achieves a response time defined by Equation 7:
At lower SCLK speeds, tread-Z1 increases, resulting in slower response times and higher cycle times.
To achieve the same cycle time, tcycle, the read time in zone 2 is given by Equation 8:
Then, the zone 2 data transfer achieves a response time defined by Equation 10:
Any increase in tread-Z2 increases response time and may increase cycle time.
For a given cycle time, the zone 1 data transfer clearly achieves faster response time, but also requires a higher SCLK speed (as evident from Equation 5, Equation 6, and Equation 7); whereas, the zone 2 data transfer clearly requires a lower SCLK speed but has a slower response time (as evident from Equation 8, Equation 9, and Equation 10). For more information about benefits of zone 2 data transfer when using isolated digital interface or MCU refer to TI TechNote - Simplify Isolation Designs Using an Enhanced-SPI ADC Interface.
For data transfer operations in zone 2 using the ADC-Clock-Master protocol
(SDO_MODE[1:0] = 11b), the device supports only the external-clock-echo option
(SSYNC_CLK_SEL[1:0] = 00b); see Table 9.