SBASAG2 December   2023 ADS9227

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: ADS9228
    10. 5.10 Typical Characteristics: ADS9227
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Data Averaging
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Frame Width
        2. 6.3.6.2 Test Patterns for Data Interface
          1. 6.3.6.2.1 User-defined Test Pattern
          2. 6.3.6.2.2 User-defined Alternating Test Pattern
          3. 6.3.6.2.3 Ramp Test Pattern
      7. 6.3.7 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2 Register Bank 1

Figure 7-12 Register Bank 1 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0Dh RESERVED DATA_FORMAT RESERVED GE_CAL_EN1 OSR_EN OSR RESERVED
12h RESERVED XOR_EN DATA_LANES
13h RESERVED RAMP_INC_ADC_A TEST_PAT_MODE_ADC_A TEST_PAT_EN_ADC_A RESERVED
14h TEST_PAT0_ADC_A
15h TEST_PAT1_ADC_A TEST_PAT0_ADC_A
16h TEST_PAT1_ADC_A
18h RESERVED RAMP_INC_ADC_B TEST_PAT_MODE_ADC_B TEST_PAT_EN_ADC_B RESERVED
19h TEST_PAT0_ADC_B
1Ah TEST_PAT1_ADC_B TEST_PAT0_ADC_B
1Bh TEST_PAT1_ADC_B
1Ch RESERVED USER_BITS_ADC_B RESERVED USER_BITS_ADC_A
33h RESERVED GE_CAL_EN3 RESERVED GE_CAL_EN2 INIT_KEY RESERVED
C0h RESERVED CLK1 OSR_INIT1 RESERVED PD_CH
C1h RESERVED PD_REF RESERVED DATA_RATE RESERVED CLK2
C4h RESERVED OSR_INIT2 RESERVED OSR_INIT3 PD_CHIP
C5h RESERVED CLK3 RESERVED
F4h RESERVED INIT RESERVED
F6h RESERVED INIT_2 RESERVED
FBh RESERVED XOR_MODE RESERVED
Table 7-2 Register Section/Block Access Type Codes
Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value

Register 0Dh (offset = Dh) [reset = 2002h]

Figure 7-13 Register 0Dh
15 14 13 12 11 10 9 8
RESERVED DATA_FORMAT RESERVED
R/W-0h R/W-1h R/W-0h
7 6 5 4 3 2 1 0
GE_CAL_EN1 OSR_EN OSR RESERVED
R/W-0h R/W-2h
Figure 7-14 Register 0Dh Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13 DATA_FORMAT R/W 1h Select data format for the ADC conversion result.
0 : Straight binary format
1 : Two's-complement format
12-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-7 GE_CAL_EN1 R/W 0h Global control for gain error calibration.
0 : Gain error calibration disabled for all channels
1 : Gain error calibration enabled for all channels
6-6 OSR_EN R/W 0h Control for data averaging depth.
0 : Data averaging disabled
1 : Data averaging enabled
5-2 OSR R/W 0h Control for enabling data averaging.
0 : 2 samples averaged
1 : 4 samples averaged
2 : 8 samples averaged
3 : 16 samples averaged
1-0 RESERVED R/W 2h Reserved. Do not change from the default reset value.

7.2.1 Register 12h (offset = 12h) [reset = 2h]

Figure 7-15 Register 12h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XOR_EN DATA_LANES
R/W-0h R/W-0h R/W-2h
Figure 7-16 Register 12h Field Descriptions
Bit Field Type Reset Description
15-4 RESERVED R/W 0h Reserved. Do not change from the default reset value.
3 XOR_EN R/W 0h Enables XOR operation on ADC conversion result.
0 : XOR operation is disabled
1 : ADC conversion result is bit-wise XOR with the LSB of the ADC conversion result
2-0 DATA_LANES R/W 2h Selects the number of output data-lanes and number of data bits per output lane.Enables XOR operation on ADC conversion result.
0 : ADC A and B data output on DOUTA and DOUTB respectively; 20bits per ADC.
2 : ADC A and B data output on DOUTA and DOUTB respectively; 24bits per ADC.
5 : ADC A and B data output on DOUTA; 20bits per ADC.
7 : ADC A and B data output on DOUTA; 24bits per ADC.

7.2.2 Register 13h (offset = 13h) [reset = 0h]

Figure 7-17 Register 13h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_ADC_A TEST_PAT_MODE_ADC_A TEST_PAT_EN_ADC_A RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-18 Register 13h Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-4 RAMP_INC_ADC_A R/W 0h Increment value for the ramp pattern output. The output ramp increments by N+1, where N is the value configured in this register.
3-2 TEST_PAT_MODE_ADC_A R/W 0h Select digital test pattern for ADC A.
0 : Fixed pattern as configured in the TEST_PAT0_ADC_A register
1 : Fixed pattern as configured in the TEST_PAT0_ADC_A register
2 : Digital ramp output
3 : Alternate fixed pattern output as configured in the
TEST_PAT0_ADC_A and TEST_PAT1_ADC_A registers
1 TEST_PAT_EN_ADC_A R/W 0h Enable digital test pattern for data corresponding to ADC A.
0 : ADC conversion result is launched on the data interface
1 : Digital test pattern is launched corresponding to ADC A on the data interface
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.3 Register 14h (offset = 14h) [reset = 0h]

Figure 7-19 Register 14h
15 14 13 12 11 10 9 8
TEST_PAT0_ADC_A[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_ADC_A[15:0]
R/W-0h
Figure 7-20 Register 14h Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT0_ADC_A[15:0] R/W 0h Lower 16 bits of test pattern 0 for ADC A corresponding to ADC A.

7.2.4 Register 15h (offset = 15h) [reset = 0h]

Figure 7-21 Register 15h
15 14 13 12 11 10 9 8
TEST_PAT1_ADC_A[7:0]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_ADC_A[23:16]
R/W-0h
Figure 7-22 Register 15h Field Descriptions
Bit Field Type Reset Description
15-8 TEST_PAT1_ADC_A[7:0] R/W 0h Lower eight bits of test pattern 1 for ADC A corresponding to ADC A.
7-0 TEST_PAT0_ADC_A[23:16] R/W 0h Upper eight bits of test pattern 0 for ADC A corresponding to ADC A.

7.2.5 Register 16h (offset = 16h) [reset = 0h]

Figure 7-23 Register 16h
15 14 13 12 11 10 9 8
TEST_PAT1_ADC_A[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT1_ADC_A[23:8]
R/W-0h
Figure 7-24 Register 16h Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT1_ADC_A[23:8] R/W 0h Upper 16 bits of test pattern 1 for ADC A corresponding to ADC A.

Register 18h (offset = 18h) [reset = 0h]

Figure 7-25 Register 18h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_ADC_B TEST_PAT_MODE_ADC_B TEST_PAT_EN_ADC_B RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-26 Register 18h Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-4 RAMP_INC_ADC_B R/W 0h Increment value for the ramp pattern output. The output ramp increments by N+1, where N is the value configured in this register.
3-2 TEST_PAT_MODE_ADC_B R/W 0h Select digital test pattern for ADC B.
0 : Fixed pattern as configured in the TEST_PAT0_ADC_B register
1 : Fixed pattern as configured in the TEST_PAT0_ADC_B register
2 : Digital ramp output
3 : Alternate fixed pattern output as configured in the
TEST_PAT0_ADC_B and TEST_PAT1_ADC_B registers
1 TEST_PAT_EN_ADC_B R/W 0h Enable digital test pattern for data corresponding to channel 5, 6, 7, and 8.
0 : ADC conversion result is launched on the data interface
1 : Digital test pattern is launched corresponding to ADC B on the data interface
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.6 Register 19h (offset = 19h) [reset = 0h]

Figure 7-27 Register 19h
15 14 13 12 11 10 9 8
TEST_PAT0_ADC_B[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_ADC_B[15:0]
R/W-0h
Figure 7-28 Register 19h Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT0_ADC_B[15:0] R/W 0h Lower 16 bits of test pattern 0 for ADC B corresponding to ADC B.

7.2.7 Register 1Ah (offset = 1Ah) [reset = 0h]

Figure 7-29 Register 1Ah
15 14 13 12 11 10 9 8
TEST_PAT1_ADC_B[7:0]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_ADC_B[23:16]
R/W-0h
Figure 7-30 Register 1Ah Field Descriptions
Bit Field Type Reset Description
15-8 TEST_PAT1_ADC_B[7:0] R/W 0h Lower eight bits of test pattern 1 for ADC B corresponding to ADC B.
7-0 TEST_PAT0_ADC_B[23:16] R/W 0h Upper eight bits of test pattern 0 for ADC B corresponding to ADC B.

7.2.8 Register 1Bh (offset = 1Bh) [reset = 0h]

Figure 7-31 Register 1Bh
15 14 13 12 11 10 9 8
TEST_PAT1_ADC_B[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT1_ADC_B[23:8]
R/W-0h
Figure 7-32 Register 1Bh Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT1_ADC_B[23:8] R/W 0h Upper 16 bits of test pattern 1 for ADC B corresponding to ADC B.

7.2.9 Register 1Ch (offset = 1Ch) [reset = 0h]

Figure 7-33 Register 1Ch
15 14 13 12 11 10 9 8
RESERVED USER_BITS_ADC_B
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED USER_BITS_ADC_A
R/W-0h R/W-0h
Figure 7-34 Register 1Ch Field Descriptions
Bit Field Type Reset Description
15-8 USER_BITS_ADC_B R/W 0h User-defined bits appended to the ADC conversion result from ADC B.
7-0 USER_BITS_ADC_A R/W 0h User-defined bits appended to the ADC conversion result from ADC A.

7.2.10 Register 33h (offset = 33h) [reset = 0h]

Figure 7-35 Register 33h
15 14 13 12 11 10 9 8
RESERVED GE_CAL_EN3 RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED GE_CAL_EN2 INIT_KEY RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-36 Register 33h Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13 GE_CAL_EN3 R/W 0h Global control for gain error calibration.
0 : Gain error calibration disabled for all channels
1 : Gain error calibration enabled for all channels
12-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6 GE_CAL_EN2 R/W 0h Global control for gain error calibration.
0 : Gain error calibration disabled for all channels
1 : Gain error calibration enabled for all channels
5-4 INIT_KEY R/W 0h Device initialization sequence access key. Write 11b to access the device initialization sequence. Write 00b for normal operation.
3-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.11 Register C0h (offset = C0h) [reset = 0h]

Figure 7-37 Register C0h
15 14 13 12 11 10 9 8
RESERVED CLK1 OSR_INIT1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED PD_CH
R/W-0h R/W-0h
Figure 7-38 Register C0h Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h Reserved. Do not change from the default reset value.
12-12 CLK1 R/W 0h Selects the clock configuration based on output data-lanes.
0 : Configuration for DATA_LANES = 0 or 2
1 : Configuration for DATA_LANES = 5 or 7
11-10 OSR_INIT1 R/W 0h Initialization for data averaging.
0 : Configuration for disabling data averaging
1 : Configuration for enabling data averaging
9-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1-0 PD_CH R/W 0h Power-down control for the analog input channels.
0 : Normal operation
1 : ADC A powered down
2 : ADC B powered down
3 : ADC A and B powered down

7.2.12 Register C1h (offset = C1h) [reset = 0h]

Figure 7-39 Register C1h
15 14 13 12 11 10 9 8
RESERVED PD_REF RESERVED DATA_RATE
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CLK2
R/W-0h R/W-0h
Figure 7-40 Register C1h Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h Reserved. Do not change from the default reset value.
11 PD_REF R/W 0h ADC reference voltage source selection.
0 : Internal reference enabled.
1 : Internal reference disabled. Connect the external reference voltage to the REFIO pin.
10-9 RESERVED R/W 0h Reserved. Do not change from the default reset value.
8 DATA_RATE R/W 0h Select data rate for the data interface.
0 : Double data rate (DDR)
1 : Single data rate (SDR)
7-1 RESERVED R/W 0h Reserved. Do not change from the default reset value.
0 CLK2 R/W 0h Select data rate for the data interface.
0 : Configuration for DATA_LANES = 2 or 7
1 : Configuration for DATA_LANES = 0 or 5

7.2.13 Register C4h (offset = C4h) [reset = 0h]

Figure 7-41 Register C4h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED OSR_INIT2 RESERVED OSR_INIT3 PD_CHIP
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-42 Register C4h Field Descriptions
Bit Field Type Reset Description
15-6 RESERVED R/W 0h Reserved. Do not change from the default reset value.
5-4 OSR_INIT2 R/W 0h Initialization for data averaging.
0 : Configuration for disabling data averaging
2 : Configuration for enabling data averaging
3-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1-1 OSR_INIT3 R/W 0h Initialization for data averaging.
0 : Configuration for disabling data averaging
1 : Configuration for enabling data averaging
0-0 PD_CHIP R/W 0h Full chip power-down control.
0 : Normal device operation
1 : Full device powered-down

7.2.14 Register C5h (offset = C5h) [reset = 0h]

Figure 7-43 Register C5h
15 14 13 12 11 10 9 8
RESERVED CLK3 RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 7-44 Register C5h Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9 CLK3 R/W 0h Select data rate for the data interface.
0 : Configuration for DATA_LANES = 0 or 2
1 : Configuration for DATA_LANES = 5 or 7

7.2.15 Register F4h (offset = F4h) [reset = 0h]

Figure 7-45 Register F4h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED CM_CTRL_EN RESERVED
R/W-0h R/W-0h R/W-0h
Figure 7-46 Register F4h Field Descriptions
Bit Field Type Reset Description
15-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1 INIT R/W 0h INIT field for device initialization. Write 1b during the initialization sequence. Write 0b for normal operation.
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.16 Register F6h (offset = F6h) [reset = 0h]

Figure 7-47 Register F6h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED INIT_2 RESERVED
R/W-0h R/W-0h R/W-0h
Figure 7-48 Register F6h Field Descriptions
Bit Field Type Reset Description
15-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1 INIT_2 R/W 0h INIT_2 field for device initialization. Write 1b during the initialization sequence. Write 0b for normal operation.
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.17 Register FBh (offset = FBh) [reset = 0h]

Figure 7-49 Register FBh
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XOR_MODE RESERVED
R/W-0h R/W-0h R/W-0h
Figure 7-50 Register FBh Field Descriptions
Bit Field Type Reset Description
15-3 RESERVED R/W 0h Reserved. Do not change from the default reset value.
2 XOR_MODE R/W 0h Selects the bit with which the ADC output data is XOR'ed when XOR output mode is enabled.
0 : PRBS bit is output after the ADC LSB. ADC output data is XOR with the PRBS bit.
1 : ADC output data is XOR with the LSB of the conversion result.
1-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.