SBASAG3A July   2023  – October 2023 AFE7728D , AFE7768D , AFE7769D

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Quad (AFE776xD) / Dual (AFE7728D) transmitters based on 0-IF up-conversion architecture:
    • Up to 650 MHz (AFE77x8D) / 730 MHz (AFE7769D) of RF transmitted DPD expansion bandwidth per chain
  • Quad (AFE776xD) / Dual (AFE7728D) receivers based on 0-IF down-conversion architecture:
    • Up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D) of RF received bandwidth per chain
  • Feedback chain based on direct RF sampling architecture:
    • Up to 650 MHz (AFE77x8D) / 730 MHz (AFE7769D) of RF observed DPD expansion bandwidth
  • Integrated CFR/DPD for PA linearization
    • Up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth
    • Up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expansion bandwidth
  • Integrated CFR/DPD for PA linearization
    • Multistage CFR with configurable cancelling pulses
    • Hardware accelerated DPD estimation engine
    • Signal Dynamics based corrector for GaN PA linearization
    • Smart data capture
  • RF frequency range: 600 MHz to 6 GHz
  • Four wideband fractional-N PLL, VCO for TX and RX LO
  • Dedicated integer-N PLL, VCO for data converters clock generation
  • JESD204B and JESD204C SerDes interface support:
    • 4 SerDes transceivers up to 29.5 Gbps
    • 8b/10b and 64b/66b encoding
    • 16-bit, 12-bit, 24-bit and 32-bit formatting
    • Subclass 1 multi-device synchronization
  • Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch