SLASF44 may   2023 AFE78201 , AFE88201

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3  Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm-Based Interrupts
        2. 7.3.3.2 Alarm Action Configuration Register
        3. 7.3.3.3 Alarm Voltage Generator
        4. 7.3.3.4 Temperature Sensor Alarm Function
        5. 7.3.3.5 Internal Reference Alarm Function
        6. 7.3.3.6 ADC Alarm Function
        7. 7.3.3.7 Fault Detection
      4. 7.3.4  IRQ
      5. 7.3.5  Internal Reference
      6. 7.3.6  Integrated Precision Oscillator
      7. 7.3.7  Precision Oscillator Diagnostics
      8. 7.3.8  One-Time Programmable (OTP) Memory
      9. 7.3.9  GPIO
      10. 7.3.10 Timer
      11. 7.3.11 Unique Chip Identifier (ID)
      12. 7.3.12 Scratch Pad Register
    4. 7.4 Device Functional Modes
      1. 7.4.1 Register Built-In Self-Test (RBIST)
      2. 7.4.2 DAC Power-Down Mode
      3. 7.4.3 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
      2. 7.5.2 GPIO Programming
      3. 7.5.3 Serial Peripheral Interface (SPI)
        1. 7.5.3.1 SPI Frame Definition
        2. 7.5.3.2 SPI Read and Write
        3. 7.5.3.3 Frame Error Checking
        4. 7.5.3.4 Synchronization
      4. 7.5.4 UART Interface
        1. 7.5.4.1 UART Break Mode (UBM)
      5. 7.5.5 Status Bits
      6. 7.5.6 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx8201 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Analog Output Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 XTR305
            1. 8.2.1.2.1.1 Current-Output Mode
            2. 8.2.1.2.1.2 Voltage Output Mode
            3. 8.2.1.2.1.3 Diagnostic Features
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1.6 DAC Register Structure and CLEAR State

The AFE88201 DAC has a 16-bit voltage output, and the AFE78201 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V.

The AFEx8201 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see Table 7-16.

Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. Figure 7-9 shows the full AFEx8201 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY.

Set the DAC to CLEAR state either by:

  1. Setting DAC_CFG.CLR.
  2. Configuring the DAC to transition to the CLEAR state in response to an alarm condition.
  3. Using the SDI pin in UBM or the SCLR pin in SPI mode as the CLEAR state input pin.

Method 1 is a direct command to the AFEx8201 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state.

Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see Table 7-25 and Section 7.3.3.2.

Method 3 supports setting the DAC to CLEAR state without writing to the AFEx8201. This pin-based DAC CLEAR state function is available in SPI mode on the SCLR pin, or in UBM on the SDI pin. The SCLR pin must be tied to GND in UBM. For details of connection options based on communication modes and pins used in each mode, see Section 7.5.1. Set the appropriate pin high to drive the DAC to CLEAR state.

GUID-20220613-SS0I-3P8Z-SRRX-MWH7J1HWVSZ1-low.svg Figure 7-7 DAC Data Path