SLLS848C April   2008  – April 2024 AM26LV31E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Complementary Out-Enable Inputs
      2. 7.3.2 High Output Impedance for Specific Driver Enable Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tPHLPropagation delay time, high- to low-level outputSee Figure 6-24812ns
tPLHPropagation delay time, low- to high-level output4812ns
ttTransition time (tr or tf)See Figure 6-2510ns
tPZHOutput-enable time to high levelSee Figure 6-31020ns
tPZLOutput-enable time to low levelSee Figure 6-41020ns
tPHZOutput-disable time from high levelSee Figure 6-31020ns
tPLZOutput-disable time from low levelSee Figure 6-41020ns
tsk(p)Pulse skewSee Figure 6-2(2)(3)0.51.5ns
tsk(o)Skew limit (pin to pin)1.5ns
tsk(lim)Skew limit (device to device)3ns
f(max)Maximum operating frequencySee Figure 6-232MHz
(1) All typical values are at VCC = 3.3V, TA = 25°C.
(2) Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
(3) Skew limit (device to device) is the maximum difference in propagation delay times between any two channels of any two devices.