SWRS314 January   2024 AWR2544

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions - Digital
    4. 6.4 Signal Descriptions - Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1 QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-64 #GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-65
      2. 7.12.2 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-236 #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-237 #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-244 #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-245 #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-70 #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-71 #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-73
      3. 7.12.3 Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1  RGMII/RMII/MII Timing Conditions
        2. 7.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 7.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 7.12.3.4  RGMII Receive Clock Timing Requirements
        5. 7.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 7.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 7.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 7.12.3.8  RMII Receive Clock Timing Requirements
        9. 7.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 7.12.3.10 MII Transmit Switching Characteristics
        11. 7.12.3.11 MII Receive Clock Timing Requirements
        12. 7.12.3.12 MII Receive Timing Requirements
        13. 7.12.3.13 MII Transmit Clock Timing Requirements
        14. 7.12.3.14 MDIO Interface Timings
      4. 7.12.4 LVDS Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5 UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-5F6D5D17-1161-44B3-ABD1-283215937B93/T4362547-185
      7. 7.12.7 Enhanced Pulse-Width Modulator (ePWM)
      8. 7.12.8 General-Purpose Input/Output
        1. 7.12.8.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-45 #GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short and Medium Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Support
  13. 12Device Nomenclature
    1. 12.1 Tools and Software
    2. 12.2 Documentation support
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • AMQ|248
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

Table 6-1 Pin Attributes (AMQ / FCCSP Package)
BALL NUMBER BALL NAME (DEFAULT) MUX SIGNAL NAME MODE TYPE BALL RESET STATE PULL UP/DOWN TYPE
U3 MSS_MIBSPIB_CS1 MSS_GPIO_12 0 IO OUTPUT DISABLED PD
MSS_MIBSPIA_HOSTIRQ 1 O
ADC_VALID 2 O
RSVD 3 I
RSVD 4 O
RSVD 5 O
MSS_MIBSPIB_CS1 6 IO
U5 MSS_GPIO_0 MSS_GPIO_13 0 IO OUTPUT DISABLED PD
MSS_GPIO_0 1 IO
PMIC_CLKOUT 2 O
MSS_EPWM_TZ2 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 IO
RSVD 7 I
RSVD 8 O
RSVD 9 O
MSS_EPWMA1 10 O
MSS_EPWMB0 11 O
RSVD 12 IO
U4 MSS_GPIO_1 MSS_GPIO_16 0 IO OUTPUT DISABLED PD
MSS_GPIO_1 1 IO
SYNC_OUT 2 O
MSS_EPWM_TZ1 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 IO
BSS_UARTA_TX 7 O
READY_INT 8 O
LVDS_VALID 9 O
RSVD 10 O
RSVD 11 O
RSVD 12 IO
MSS_MIBSPIB_CS1 13 IO
RSVD 14 IO
MSS_EPWMA_SYNCI 15 I
T3 MSS_MIBSPIB_SDO MSS_GPIO_21 0 IO OUTPUT DISABLED PU
MSS_MIBSPIB_SDO 1 IO
MSS_I2CA_SDA 2 IO
MSS_EPWMA0 3 O
RSVD 4 O
RSVD 5 O
RSVD 6 I
RSVD 7 IO
U2 MSS_MIBSPIB_SDI MSS_GPIO_22 0 IO OUTPUT DISABLED PU
MSS_MIBSPIB_SDI 1 IO
MSS_I2CA_SCL 2 IO
MSS_EPWMB0 3 O
RSVD 4 O
RSVD 5 O
RSVD 6 IO
RSVD 7 IO
R1 MSS_MIBSPIB_CLK MSS_GPIO_5 0 IO OUTPUT DISABLED PU
MSS_MIBSPIB_CLK 1 IO
MSS_UARTA_RX 2 IO
MSS_EPWMC0 3 O
RSVD 4 O
RSVD 5 O
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
RSVD 8 IO
T1 MSS_MIBSPIB_CS0 MSS_GPIO_4 0 IO OUTPUT DISABLED PU
MSS_MIBSPIB_CS0 1 IO
MSS_UARTA_TX 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
RSVD 8 IO
RSVD 9 IO
U8 MSS_QSPI_0 MSS_GPIO_8 0 IO OUTPUT DISABLED PD
MSS_QSPI_0 1 IO
MSS_MIBSPIB_MISO 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 O
RSVD 7 O
U7 MSS_QSPI_1 MSS_GPIO_9 0 IO OUTPUT DISABLED PD
MSS_QSPI_1 1 I
MSS_MIBSPIB_MOSI 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 O
RSVD 7 O
MSS_MIBSPIB_CS2 8 IO
U6 MSS_QSPI_2 MSS_GPIO_10 0 IO OUTPUT DISABLED PU
MSS_QSPI_2 1 I
ADC_VALID 2 O
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 O
RSVD 7 O
RSVD 8 IO
T5 MSS_QSPI_3 MSS_GPIO_11 0 IO OUTPUT DISABLED PU
MSS_QSPI_3 1 I
ADC_VALID 2 O
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 O
RSVD 7 O
RSVD 8 IO
T7 MSS_QSPI_CLK MSS_GPIO_7 0 IO OUTPUT DISABLED PD
MSS_QSPI_CLK 1 IO
MSS_MIBSPIB_CLK 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 IO
T6 MSS_QSPI_CS MSS_GPIO_6 0 IO OUTPUT DISABLED PU
MSS_QSPI_CS 1 O
MSS_MIBSPIB_CS0 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
B17 WARM_RESET WARM_RESET 0 IO HI-Z (OPEN DRAIN)
D17 NERROR_OUT NERROR_OUT 0 IO HI-Z (OPEN DRAIN)
B6 TCK MSS_GPIO_17 0 IO OUTPUT DISABLED PD
TCK 1 I
MSS_UARTB_TX 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
BSS_UARTA_RX 6 I
RSVD 7 I
RSVD 8 IO
B5 TMS MSS_GPIO_18 0 IO OUTPUT DISABLED PU
TMS 1 IO
BSS_UARTA_TX 2 O
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 IO
B8 TDI MSS_GPIO_23 0 IO OUTPUT DISABLED PU
TDI 1 I
MSS_UARTA_RX 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 I
RSVD 7 IO
B7 TDO MSS_GPIO_24 0 IO OUTPUT DISABLED HI-Z
TDO 1 O
MSS_UARTA_TX 2 IO
RSVD 3 I
RSVD 4 O
RSVD 5 O
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
RSVD 8 O
RSVD 9 IO
A9 MCU_CLKOUT MSS_GPIO_25 0 IO OUTPUT DISABLED PD
MCU_CLKOUT 1 O
TRACE_CLK 2 O
RSVD 3 I
RSVD 4 O
RSVD 5 O
RSVD 6 I
FRAME_START 7 O
READY_INT 8 O
LVDS_VALID 9 O
BSS_UARTA_RX 10 I
RSVD 11 O
MSS_EPWMA0 12 O
RSVD 13 O
RSVD 14 IO
OBS_CLKOUT 15 O
T4 MSS_GPIO_2 MSS_GPIO_26 0 IO OUTPUT DISABLED PD
MSS_GPIO_2 1 IO
RSVD 2 O
RSVD 3 IO
RSVD 4 O
RSVD 5 O
RSVD 6 IO
MSS_UARTB_TX 7 IO
MSS_GPIO_2 8 IO
SYNC_OUT 9 O
PMIC_CLKOUT 10 O
CHIRP_START 11 O
CHIRP_END 12 O
FRAME_START 13 O
MSS_EPWM_TZ0 14 I
LVDS_VALID 15 O
B10 PMIC_CLKOUT MSS_GPIO_27 0 IO OUTPUT DISABLED HI-Z
PMIC_CLKOUT 1 O
OBS_CLKOUT 2 O
TRACE_CTL 3 O
RSVD 4 O
RSVD 5 O
CHIRP_START 6 O
CHIRP_END 7 O
FRAME_START 8 O
READY_INT 9 O
LVDS_VALID 10 O
MSS_EPWMA1 11 O
MSS_EPWMB0 12 O
RSVD 13 IO
C17 HW_SYNCIN MSS_GPIO_28 0 IO OUTPUT DISABLED PD
HW_SYNCIN 1 I
ADC_VALID 2 O
RSVD 3 IO
RSVD 4 O
RSVD 5 O
MSS_UARTB_RX 6 IO
RSVD 7 IO
RSVD 8 IO
SYNC_OUT 9 O
T2 MSS_MIBSPIB_CS2 MSS_GPIO_29 0 IO OUTPUT DISABLED HI-Z
SYNC_OUT 1 O
RCOSC_CLK 2 O
RSVD 3 IO
RSVD 4 O
RSVD 5 O
READY_INT 6 O
LVDS_VALID 7 O
RSVD 8 O
RSVD 9 IO
MSS_MIBSPIB_CS1 10 IO
MSS_MIBSPIB_CS2 11 IO
MSS_EPWMB0 12 O
MSS_EPWMB1 13 O
A11 MSS_RS232_RX MSS_GPIO_15 0 IO OUTPUT DISABLED PU
MSS_RS232_RX 1 IO
MSS_UARTA_RX 2 IO
RSVD 4 O
RSVD 5 O
BSS_UARTA_TX 6 O
MSS_UARTB_RX 7 IO
RSVD 8 IO
MSS_I2CA_SCL 9 IO
MSS_EPWMB0 10 O
MSS_EPWMB1 11 O
MSS_EPWMC0 12 O
A16 MSS_RS232_TX MSS_GPIO_14 0 IO OUTPUT DISABLED PU
MSS_RS232_TX 1 IO
RSVD 3 O
RSVD 4 O
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
BSS_UARTA_TX 7 O
READY_INT 8 O
LVDS_VALID 9 O
RSVD 10 IO
MSS_I2CA_SDA 11 IO
MSS_EPWMA0 12 O
MSS_EPWMA1 13 O
RSVD 14 IO
MSS_EPWMB0 15 O
A6 MSS_GPIO_31 TRACE_DATA_0 0 O OUTPUT DISABLED PD
MSS_GPIO_31 1 IO
RSVD 2 IO
RSVD 3 I
MSS_UARTA_TX 4 IO
RSVD 5 I
MSS_GPIO_31 6 IO
RSVD 7 IO
RSVD 8 I
RSVD 9 I
MSS_I2CA_SDA 10 IO
A10 MSS_GPIO_30 TRACE_DATA_1 0 O OUTPUT DISABLED PD
MSS_GPIO_30 1 IO
RSVD 2 IO
MSS_EPWMC_SYNCI 3 I
MSS_UARTA_RX 4 IO
RSVD 5 I
MSS_GPIO_0 6 IO
RSVD 7 IO
RSVD 8 I
RSVD 9 I
MSS_I2CA_SCL 10 IO
B9 MSS_GPIO_8 TRACE_DATA_2 0 O OUTPUT DISABLED PD
MSS_GPIO_29 1 IO
RSVD 2 IO
MSS_EPWMB_SYNCI 3 I
RSVD 4 I
RSVD 5 I
MSS_GPIO_1 6 IO
MSS_GPIO_8 7 IO
MSS_EPWMA0 8 O
MSS_CPTS0_TS_GENF0 9 O
CHIRP_START 10 O
CHIRP_END 11 O
FRAME_START 12 O
READY_INT 13 O
ADC_VALID 14 O
B11 MSS_GPIO_9 TRACE_DATA_3 0 O OUTPUT DISABLED PD
MSS_GPIO_28 1 IO
RSVD 2 IO
RSVD 3 I
MSS_EPWMC_SYNCO 4 O
RSVD 5 I
MSS_GPIO_2 6 IO
MSS_GPIO_9 7 IO
MSS_EPWMA1 8 O
MSS_CPTS0_TS_GENF1 9 O
CHIRP_START 10 O
CHIRP_END 11 O
FRAME_START 12 O
READY_INT 13 O
ADC_VALID 14 O
A7 MSS_GPIO_3 TRACE_DATA_4 0 O OUTPUT DISABLED PD
MSS_GPIO_3 1 IO
RSVD 2 IO
RSVD 3 I
MSS_EPWMB_SYNCO 4 O
RSVD 5 I
MSS_GPIO_27 6 IO
MSS_EPWMB0 7 O
MSS_CPTS0_TS_GENF2 8 O
XREF_CLK1 9 I
MSS_CPTS0_TS_GENF1 10 O
MSS_CPTS0_HW1TSPUSH 11 I
ADC_VALID 12 O
A8 MSS_GPIO_4 TRACE_DATA_5 0 O OUTPUT DISABLED PD
MSS_GPIO_4 1 IO
RSVD 2 IO
RSVD 3 I
MSS_EPWM_TZ2 4 I
MSS_UARTB_TX 5 IO
MSS_GPIO_26 6 IO
MSS_EPWMB1 7 O
MSS_CPTS0_TS_COMP 8 O
XREF_CLK0 9 I
MSS_CPTS0_HW2TSPUSH 10 I
READY_INT 11 O
B18 BSS_UARTA_TX TRACE_DATA_6 0 O OUTPUT DISABLED PD
MSS_GPIO_5 1 IO
RSVD 2 IO
RSVD 3 I
MSS_EPWM_TZ1 4 I
BSS_UARTA_TX 5 O
MSS_GPIO_25 6 IO
MSS_GPIO_10 7 IO
MSS_EPWMC0 8 O
MSS_CPTS0_TS_GENF2 9 O
MSS_CPTS0_HW1TSPUSH 10 I
CHIRP_START 11 O
A17 MSS_GPIO_11 TRACE_DATA_7 0 O OUTPUT DISABLED PD
MSS_GPIO_6 1 IO
RSVD 2 IO
RSVD 3 I
MSS_EPWM_TZ0 4 I
RSVD 5 IO
MSS_GPIO_24 6 IO
MSS_GPIO_11 7 IO
MSS_EPWMC1 8 O
MSS_CPTS0_TS_COMP 9 O
MSS_CPTS0_TS_GENF0 10 O
MSS_CPTS0_HW2TSPUSH 11 I
CHIRP_END 12 O
T13 MSS_GPIO_17 MSS_GPIO_17 0 IO OUTPUT DISABLED PD
MSS_MII_COL 1 I
MSS_RMII_REFCLK 2 IO
RSVD 3 I
RSVD 4 IO
RSVD 5 I
MSS_EPWMA1 6 O
T12 MSS_I2CA_SDA MSS_GPIO_18 0 IO HI-Z
MSS_MII_CRS 1 I
MSS_RMII_CRS_DV 2 I
MSS_I2CA_SDA 3 IO
RSVD 4 IO
RSVD 5 I
MSS_EPWMB1 6 O
R12 MSS_I2CA_SCL MSS_GPIO_19 0 IO HI-Z
MSS_MII_RXER 1 I
MSS_RMII_RXER 2 I
MSS_I2CA_SCL 3 IO
RSVD 4 IO
RSVD 5 I
MSS_EPWMC1 6 O
M17 MSS_RGMII_TCTL MSS_GPIO_20 0 IO OUTPUT DISABLED PD
MSS_MII_TXEN 1 O
MSS_RMII_TXEN 2 O
MSS_RGMII_TCTL 3 O
RSVD 4 IO
RSVD 5 I
MSS_EPWMA0 6 O
U16 MSS_RGMII_RCTL MSS_GPIO_21 0 IO HI-Z
MSS_MII_RXDV 1 I
RSVD 2 I
MSS_RGMII_RCTL 3 I
MSS_UARTB_RX 5 IO
MSS_EPWMB0 6 O
N17 MSS_RGMII_TD3 MSS_GPIO_22 0 IO OUTPUT DISABLED PD
MSS_MII_TXD3 1 O
RSVD 2 I
MSS_RGMII_TD3 3 O
RSVD 4 IO
MSS_UARTB_TX 5 IO
MSS_EPWMC0 6 O
T18 MSS_RGMII_TD2 MSS_GPIO_23 0 IO OUTPUT DISABLED PD
MSS_MII_TXD2 1 O
RSVD 2 I
MSS_RGMII_TD2 3 O
P17 MSS_RGMII_TD1 MSS_GPIO_24 0 IO OUTPUT DISABLED PD
MSS_MII_TXD1 1 O
MSS_RMII_TXD1 2 O
MSS_RGMII_TD1 3 O
R17 MSS_RGMII_TD0 MSS_GPIO_25 0 IO OUTPUT DISABLED PD
MSS_MII_TXD0 1 O
MSS_RMII_TXD0 2 O
MSS_RGMII_TD0 3 O
T17 MSS_RGMII_TCLK MSS_GPIO_26 0 IO OUTPUT DISABLED PD
MSS_MII_TXCLK 1 I
RSVD 2 I
MSS_RGMII_TCLK 3 O
U15 MSS_RGMII_RCLK MSS_GPIO_27 0 IO OUTPUT DISABLED PD
MSS_MII_RXCLK 1 I
RSVD 2 I
MSS_RGMII_RCLK 3 I
U17 MSS_RGMII_RD3 MSS_GPIO_28 0 IO HI-Z
MSS_MII_RXD3 1 I
RSVD 2 I
MSS_RGMII_RD3 3 I
R16 MSS_RGMII_RD2 MSS_GPIO_29 0 IO HI-Z
MSS_MII_RXD2 1 I
RSVD 2 I
MSS_RGMII_RD2 3 I
T16 MSS_RGMII_RD1 MSS_GPIO_30 0 IO HI-Z
MSS_MII_RXD1 1 I
MSS_RMII_RXD1 2 I
MSS_RGMII_RD1 3 I
T15 MSS_RGMII_RD0 MSS_GPIO_31 0 IO HI-Z
MSS_MII_RXD0 1 I
MSS_RMII_RXD0 2 I
MSS_RGMII_RD0 3 I
T14 MSS_MDIO_DATA MSS_GPIO_30 0 IO OUTPUT DISABLED PU
MSS_MDIO_DATA 1 IO
RSVD 2 I
RSVD 3 I
U14 MSS_MDIO_CLK MSS_GPIO_31 0 IO OUTPUT DISABLED PU
MSS_MDIO_CLK 1 O
RSVD 2 I
RSVD 3 I
P1 MSS_UARTA_RX MSS_GPIO_12 0 IO OUTPUT DISABLED PU
MSS_CPTS0_TS_SYNC 1 O
RSVD 2 I
MSS_GPIO_8 3 IO
MSS_UARTB_RX 4 IO
MSS_UARTA_RX 5 IO
RSVD 6 IO
R2 MSS_UARTA_TX MSS_GPIO_13 0 IO HI-Z
MSS_CPTS0_HW2TSPUSH 1 I
RSVD 2 I
MSS_GPIO_9 3 IO
MSS_UARTB_TX 4 IO
MSS_UARTA_TX 5 IO
RSVD 6 IO
P2 MSS_UARTB_TX MSS_GPIO_0 0 IO HI-Z
RSVD 1 IO
RSVD 2 I
MSS_EPWMB_SYNCI 3 I
RSVD 4 IO
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
RSVD 7 I
LVDS_VALID 8 O
RSVD 9 I
RSVD 10 I
RSVD 11 I
MSS_GPIO_31 12 IO