SLUSEC9A
October 2020 – March 2021
BQ25618E
,
BQ25619E
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Power-On-Reset (POR)
9.3.2
Device Power Up From Battery Without Input Source
9.3.3
Power Up From Input Source
9.3.3.1
Power Up REGN LDO
9.3.3.2
Poor Source Qualification
9.3.3.3
Input Source Type Detection (IINDPM Threshold)
9.3.3.3.1
PSEL Pins Sets Input Current Limit
9.3.3.4
Input Voltage Limit Threshold Setting (VINDPM Threshold)
9.3.3.5
Power Up Converter in Buck Mode
9.3.3.6
HIZ Mode with Adapter Present
9.3.4
Power Path Management
9.3.4.1
Narrow Voltage DC (NVDC) Architecture
9.3.4.2
Dynamic Power Management
9.3.4.3
Supplement Mode
9.3.5
Battery Charging Management
9.3.5.1
Autonomous Charging Cycle
9.3.5.2
Battery Charging Profile
9.3.5.3
Charging Termination
9.3.5.4
Thermistor Qualification
9.3.5.4.1
JEITA Guideline Compliance During Charging Mode
9.3.5.5
Charging Safety Timer
9.3.6
Ship Mode and QON Pin
9.3.6.1
BATFET Disable (Enter Ship Mode)
9.3.6.2
BATFET Enable (Exit Ship Mode)
9.3.6.3
BATFET Full System Reset
9.3.7
Status Outputs ( STAT, INT , PG )
9.3.7.1
Power Good Indicator (PG_STAT Bit; BQ25619E only)
9.3.7.2
Charging Status Indicator (STAT)
9.3.7.3
Interrupt to Host ( INT)
9.3.8
Protections
9.3.8.1
Voltage and Current Monitoring in Buck Mode
9.3.8.1.1
Input Overvoltage Protection (ACOV)
9.3.8.1.2
System Overvoltage Protection (SYSOVP)
9.3.8.2
Thermal Regulation and Thermal Shutdown
9.3.8.2.1
Thermal Protection in Buck Mode
9.3.8.3
Battery Protection
9.3.8.3.1
Battery Overvoltage Protection (BATOVP)
9.3.8.3.2
Battery Overdischarge Protection
9.3.8.3.3
System Overcurrent Protection
9.3.9
Serial Interface
9.3.9.1
Data Validity
9.3.9.2
START and STOP Conditions
9.3.9.3
Byte Format
9.3.9.4
Acknowledge (ACK) and Not Acknowledge (NACK)
9.3.9.5
Slave Address and Data Direction Bit
9.3.9.6
Single Read and Write
9.3.9.7
Multi-Read and Multi-Write
9.4
Device Functional Modes
9.4.1
Host Mode and Default Mode
9.5
Register Maps
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Inductor Selection
10.2.2.2
Input Capacitor and Resistor
10.2.2.3
Output Capacitor
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Support Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTW|24
MPQF167C
Thermal pad, mechanical data (Package|Pins)
RTW|24
QFND125K
Orderable Information
slusec9a_oa
slusec9a_pm
13.1
Device Support