SLUSCH6B March   2016  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 PSEL Pin Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Power Path Management
        1. 8.2.4.1 Dynamic Power Management
      5. 8.2.5  Battery Charging Management
        1. 8.2.5.1 Autonomous Charging Cycle
        2. 8.2.5.2 Battery Charging Profile
        3. 8.2.5.3 Charging Termination
        4. 8.2.5.4 Charging Safety Timer
      6. 8.2.6  Battery Monitor
      7. 8.2.7  Status Outputs (PG, STAT, and INT)
        1. 8.2.7.1 Power Good Indicator (PG)
        2. 8.2.7.2 Charging Status Indicator (STAT)
        3. 8.2.7.3 Interrupt to Host (INT)
      8. 8.2.8  Thermal Regulation and Thermal Shutdown
        1. 8.2.8.1 Thermal Protection in Buck Mode
      9. 8.2.9  Voltage and Current Monitoring in Buck
        1. 8.2.9.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.9.1.1 Input Overvoltage (ACOV)
          2. 8.2.9.1.2 System Overvoltage Protection (SYSOVP)
      10. 8.2.10 Battery Protection
        1. 8.2.10.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.10.2 Battery Over-Discharge Protection
      11. 8.2.11 Serial Interface
        1. 8.2.11.1 Data Validity
        2. 8.2.11.2 START and STOP Conditions
        3. 8.2.11.3 Byte Format
        4. 8.2.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.11.5 Slave Address and Data Direction Bit
        6. 8.2.11.6 Single Read and Write
        7. 8.2.11.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Map
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG11
      18. 8.4.18 REG12
      19. 8.4.19 REG13
      20. 8.4.20 REG14
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

YFF Package
42-Pin DSBGA
Top View
bq25898C pinout_slusch6.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
VBUS E3-G3 P Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
PSEL C3 DI Power source selection input. High indicates a USB host source and Low indicates an adapter source.
PG D3 DO Open drain active low power good indicator. Connect to the pull up rail via 10-kohm resistor. LOW indicates a good input source if the input voltage is within VVBUS_OP, above SLEEP mode threshold (VSLEEPZ), and current limit is above IBATSRC (30mA).
STAT G1 DO Open-drain interrupt output. Connect to the INT to a logic rail via 10-kohm resistor. The INT pin sends active low, 256-us pulse to host to report charger device status and fault.
SCL A3 DI I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA B3 DIO I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
INT F2 DO Open-drain Interrupt Output. Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-μs pulse to host to report charger device status and fault.
CE B4 DI Active low charge enable pin. Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low.
NC B5-B6 No connect. Float the pin.
BAT A1-E1 P Battery connection point to the positive terminal of the battery pack. The internal current sensing circuitry is connected between SYS and BAT. Connect a 10uF closely to the BAT pin.
SYS A2-E2 P Converter output connection point. The internal current sensing circuitry is connected between SYS and BAT. Connect a 20uF closely to the SYS pin.
PGND C4,C6-G6,A4,G2 P Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin.
SW C5-G5 P Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047μF bootstrap capacitor from SW to BTST.
BTST A6 P PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boost-strap diode. Connect the 0.047μF bootstrap capacitor from SW to BTST.
REGN A5 P PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7μF (10 V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.
PMID D4-G4 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Given the total input capacitance, put 1μF on VBUS to PGND, and the rest capacitance on PMID to PGND.
BATSEN F1 AI Remote battery sense input. The typical pin resistance is 800 kΩ. Connect as close to battery as possible.
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)