SLUSBD6D July   2013  – July 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Principles of Operation
        1. 7.3.1.1 Fundamentals
        2. 7.3.1.2 Wireless Power Consortium (WPC)
        3. 7.3.1.3 Power Transfer
        4. 7.3.1.4 Communication
      2. 7.3.2 Dynamic Power Limiting
      3. 7.3.3 Shut Down Through External Thermal Sensor or Trigger
      4. 7.3.4 Fault Handling and Indication
      5. 7.3.5 Power Transfer Start Signal
      6. 7.3.6 Power On Reset
      7. 7.3.7 External Reset, RESET Pin
      8. 7.3.8 Trickle Charge and CS100
    4. 7.4 Device Functional Modes
      1. 7.4.1 LED Indication Modes
      2. 7.4.2 Low Power Mode
    5. 7.5 Programming
      1. 7.5.1 Option Select Pins
      2. 7.5.2 Current Monitoring Requirements
      3. 7.5.3 All Unused Pins
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 PMOD, FOD, and FOD Calibration
        2. 8.2.2.2 Coils and Matching Capacitors
        3. 8.2.2.3 Design Checklist for WPC1.1 Compliance With the bq500212A
        4. 8.2.2.4 Input Regulator
        5. 8.2.2.5 Power Train
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

A good PCB layout is critical to proper system operation. There are many references on proper PCB layout techniques.

Generally speaking, the system layout requires a 4-layer PCB layout, although a 2-layer PCB layout can be achieved. The following list is a proven and recommended approach to the layer stack-up:

  • Layer 1, component placement and as much ground plane as possible
  • Layer 2, clean ground
  • Layer 3, finish routing
  • Layer 4, clean ground

Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise free voltage reference plane for device operation.

Keep as much copper as possible. Make sure the bq500212A GND pins and the power pad have a continuous flood connection to the ground plane. The power pad must also be stitched to the ground plane, which also acts as a heat sink for the bq500212A device. A good GND reference is necessary for proper bq500212A operation, such as analog-digital conversion, clock stability and best overall EMI performance.

Separate the analog ground plane from the power ground plane and use only one tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds.

The COMM return signal from the resonant tank must be routed as a differential pair. This is intended to reduce stray noise induction. The frequencies of concern warrant low-noise analog signaling techniques, such as differential routing and shielding, but the COMM signal lines do not need to be impedance matched.

Typically a single-chip controller solution with integrated power FET and synchronous rectifier is used. To create a tight loop, pull in the buck inductor and power loop as close as possible. Likewise, the power train, full-bridge components must be pulled together as tight as possible. See the bq500212AEVM-550, bqTESLA Wireless Power TX EVM User's Guide (SLVU536) for layout examples.

Use a ground flood connection for the ground plane under the device. Connect the device ground pins to the thermal pad. Flow the ground plane between the thermal pad and top layer ground. Use multiple vias to connect the thermal pad to the internal ground layer. Verify that the solder mask under the device is removed for good connection to the thermal pad.

The customer must choose a full-bridge option to design the power section. Figure 13, based on the bq500212A EVM, uses a power stage device, which is an integrated drive and two MOSFETs.

10.2 Layout Example

bq500212A IC.gif Figure 12. bq500212A IC Ground Connections
bq500212A PWR.gif Figure 13. bq500212A Power Section Using CSD9794Q4M or CSD97376Q4M Power Stage