SLUSAM9E July   2011  – April 2020 BQ76925

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Internal Power Control (Startup and Shutdown)
    7. 7.7  3.3-V Voltage Regulator
    8. 7.8  Voltage Reference
    9. 7.9  Cell Voltage Amplifier
    10. 7.10 Current Sense Amplifier
    11. 7.11 Overcurrent Comparator
    12. 7.12 Internal Temperature Measurement
    13. 7.13 Cell Balancing and Open Cell Detection
    14. 7.14 I2C Compatible Interface
    15. 7.15 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO Voltage Regulator
      2. 8.3.2 ADC Interface
        1. 8.3.2.1 Reference Voltage
          1. 8.3.2.1.1 Host ADC Calibration
        2. 8.3.2.2 Cell Voltage Monitoring
          1. 8.3.2.2.1 Cell Amplifier Headroom Under Extreme Cell Imbalance
          2. 8.3.2.2.2 Cell Amplifier Headroom Under BAT Voltage Drop
        3. 8.3.2.3 Current Monitoring
        4. 8.3.2.4 Overcurrent Monitoring
        5. 8.3.2.5 Temperature Monitoring
          1. 8.3.2.5.1 Internal Temperature Monitoring
      3. 8.3.3 Cell Balancing and Open Cell Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 POWER ON RESET (POR)
        2. 8.4.1.2 STANDBY
        3. 8.4.1.3 SLEEP
    5. 8.5 Programming
      1. 8.5.1 Host Interface
        1. 8.5.1.1 I2C Addressing
        2. 8.5.1.2 Bus Write Command to BQ76925
        3. 8.5.1.3 Bus Read Command from BQ76925 Device
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 Voltage, Current, and Temperature Outputs
        2. 9.1.1.2 Power Management
        3. 9.1.1.3 Low Dropout (LDO) Regulator
        4. 9.1.1.4 Input Filters
        5. 9.1.1.5 Output Filters
      2. 9.1.2 Cell Balancing
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.14 I2C Compatible Interface

PARAMETERS MIN TYP MAX UNIT
DC PARAMETERS
VIL Input Low Logic Threshold 0.6 V
VIH Input High Logic Threshold 2.8 V
VOL Output Low Logic Drive IOL = 1 mA 0.20 V
IOL = 2.5 mA 0.40
VOH Output High Logic Drive (Not applicable due to open-drain outputs) N/A V
ILKG I2C Pin Leakage Pin = 5 V, Output in Hi-Z < 1 µA
AC PARAMETERS
tr SCL, SDA　Rise Time 1000 ns
tf SCL, SDA　Fall Time 300 ns
tw(H) SCL Pulse Width High 4 µs
tw(L) SCL Pulse Width Low 4.7 µs
tsu(STA) Setup time for START condition 4.7 µs
th(STA) START condition hold time after which first clock pulse is generated 4 µs
tsu(DAT) Data setup time 250 ns
th(DAT) Data hold time 0(1) µs
tsu(STOP) Setup time for STOP condition 4 µs
tsu(BUF) Time the bus must be free before new transmission can start 4.7 µs
t V Clock Low to Data Out Valid 900 ns
th(CH) Data Out Hold Time After Clock Low 0 ns
fSCL Clock Frequency 0 100 kHz
tWAKE I2C ready after transition to Wake Mode 2.5 ms
(1) Devices must provide internal hold time of at least 300 ns for the SDA signal-to-bridge of the undefined region of the falling edge of SCL.
BQ76925 I2C_time_lusam9.gifFigure 1. I2C Timing