SLUSAX1G December   2012  – July 2018

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sense Positive Input for Vx
      2. 8.3.2 Output Drive, OUT
      3. 8.3.3 Supply Input, VDD
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 OVERVOLTAGE Mode
      3. 8.4.3 Customer Test Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Application Curves
    2. 9.2 Systems Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

DPJ Package
8-Pin (WSON)
Top View

Pin Functions

NO. NAME TYPE I/O DESCRIPTION
1 VDD P Power supply
2 V5 I Sense input for positive voltage of the fifth cell from the bottom of the stack
3 V4 I Sense input for positive voltage of the fourth cell from the bottom of the stack
4 V3 I Sense input for positive voltage of the third cell from the bottom of the stack
5 V2 I Sense input for positive voltage of the second cell from the bottom of the stack
6 V1 I Sense input for positive voltage of the lowest cell in the stack
7 VSS P Electrically connected to IC ground and negative terminal of the lowest cell in the stack
8 OUT O Output drive for overvoltage fault signal