SCHS328B January   2003  – April 2024 CD54AC138 , CD74AC138

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics, VCC = 1.5V
    7. 4.7 Switching Characteristics, VCC = 3.3V ± 0.3V
    8. 4.8 Switching Characteristics, VCC = 5V ± 0.5V
    9. 4.9 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • J|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Designed specifically for high-speed memory decoders and data-transmission systems
  • Incorporate three enable inputs to simplify cascading and/or data reception
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F Devices
  • SCR-latchup-resistant CMOS process and circuit design
  • Exceeds 2kV ESD protection per MIL-STD-883, method 3015