SCHS141J March   1998  – October 2022 CD54HC112 , CD54HCT112 , CD74HC112 , CD74HCT112

PRODMIX  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

tr, tf = 6 ns
PARAMETER VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL Propagation delay,
CLK to Q, Q		 2 175 220 265 ns
4.5 14(3) 35 44 53
6 30 37 45
tPLH, tPHL Propagation delay,
PRE to Q, Q		 2 155 195 235 ns
4.5 13(3) 31 39 47
6 26 33 40
tPLH, tPHL Propagation delay,
CLR to Q, Q		 2 180 225 270 ns
4.5 15(3) 36 45 54
6 31 38 46
tTLH, tTHL Output transition time 2 75 95 110 ns
4.5 15 19 22
6 13 16 19
CI Input capacitance 10 10 10 pF
fMAX CLK frequency 5 60(3) MHz
CPD Power dissipation capacitance(1)(2) 5 12(4) pF
HCT TYPES
tPLH, tPHL Propagation delay,
CLK to Q, Q		 4.5 14(3) 35 44 53 ns
tPLH, tPHL Propagation delay,
PRE to Q, Q		 4.5 13(3) 32 40 48 ns
tPLH, tPHL Propagation delay,
CLR to Q, Q		 4.5 14(3) 37 46 56 ns
tTLH, tTHL Output transition time 4.5 15 19 22 ns
CI Input capacitance 10 10 10 pF
fMAX CLK frequency 5 60(3) MHz
CPD Power dissipation capacitance(1)(2) 5 20(4) pF
(1) CPD is used to determine the dynamic power consumption, per flip-flop.
(2) PD = CPD VCC2 fi + ∑ CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
(3) CL = 15 pF and VCC = 5 V.
(4) VCC = 5 V.