SCHS353A January   2004  – February 2022 CD74HC595

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
    1.     5
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6.     12
    7. 5.6 Switching Characteristics
    8. 5.7 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • NS|16
  • DW|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The CD74HC595 is an 8-bit serial-input parallel-output shift register with output registers and 3-state outputs.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD74HC595E PDIP (16) 19.31 mm × 6.35 mm
CD74HC595DW SOIC-DW (16) 10.30 mm × 7.50 mm
CD74HC595M SOIC-D (16) 9.90 mm × 3.90 mm
CD74HC595NS SO (16) 10.20 mm × 5.30 mm
CD74HC595SM SSOP (16) 6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20211015-SS0I-66P0-J2PR-6DVV9SDRTXZD-low.gif Functional Block Diagram