SCAS892C February   2010  – December 2016 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Control Terminal Setting
      2. 10.3.2 Default Device Setting
    4. 10.4 Device Functional Modes
      1. 10.4.1 SDA and SCL Serial Interface
    5. 10.5 Programming
      1. 10.5.1 Data Protocol
      2. 10.5.2 Command Code Definition
      3. 10.5.3 Generic Programming Sequence
      4. 10.5.4 Byte Write Programming Sequence
      5. 10.5.5 Byte Read Programming Sequence
      6. 10.5.6 Block Write Programming Sequence
      7. 10.5.7 Block Read Programming Sequence
      8. 10.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 10.5.9 SDA and SCL Hardware Interface
    6. 10.6 Register Maps
      1. 10.6.1 SDA and SCL Configuration Registers
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Spread-Spectrum Clock (SSC)
        2. 11.2.2.2 PLL Multiplier or Divider Definition
        3. 11.2.2.3 Crystal Oscillator Start-Up
        4. 11.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 11.2.2.5 Unused Inputs and Outputs
        6. 11.2.2.6 Switching Between XO and VCXO Mode
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Layout

13.1 Layout Guidelines

When the CDCEx937-Q1 device is used as a crystal buffer, any parasitics across the crystal affect the pulling range of the VCXO. Therefore, take care in placing the crystal units on the board. Crystals must be placed as close to the device as possible, ensuring that the routing lines from the crystal terminals to Xin and Xout have the same length.

If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise coupling.

Additional discrete capacitors can be required to meet the load capacitance specification of certain crystals. For example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can range from 0 pF to 20 pF with steps of 1 pF. Therefore, the 0.7-pF capacitor can be discretely added on top of an internal 10 pF.

To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the device as possible and symmetrically with respect to Xin and Xout.

Figure 23 shows a conceptual layout detailing recommended placement of power-supply bypass capacitors. For component-side mounting, use 0402 body-size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low-impedance connection to the ground plane.

13.2 Layout Example

CDCE937-Q1 CDCEL937-Q1 layout_example_scas892.gif Figure 23. CDCE937-Q1 Layout Example