SCAS844G August   2007  – January 2024 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 PW Package24-Pin TSSOP(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
GND 5, 9, 14, 20 G Ground
SCL/S2 22 I SCL: Serial clock input (default configuration), LVCMOS; internal pullup 500 kΩ; or
S2: User-programmable control input; LVCMOS inputs; internal pullup 500 kΩ
SDA/S1 23 I/O SDA: Bidirectional serial data input/output (default configuration), LVCMOS; internal pullup 500 kΩ; or
S1: User-programmable control input; LVCMOS inputs; internal pullup 500 kΩ
S0 2 I User-programmable control input S0; LVCMOS inputs; internal pullup 500 kΩ
VCtrl 4 I VCXO control voltage (leave open or pull up when not used)
VDD 3, 13 P 1.8-V power supply for the device
VDDOUT 6, 10, 17 P CDCEL949: 1.8-V supply for all outputs
CDCE949: 3.3-V or 2.5-V supply for all outputs
Xin/CLK 1 I Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus)
Xout 24 O Crystal oscillator output (leave open or pull up when not used)
Y1 21 O LVCMOS output
Y2 19
Y3 18
Y4 7
Y5 8
Y6 16
Y7 15
Y8 11
Y9 12
(1) G = Ground, I = Input, O = Output, P = Power