3 Description
The CDCE937 and CDCEL937 devices are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 7 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to three independent configurable PLLs.
The CDCEx937 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937 and to 2.5 V to 3.3 V for CDCE937.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal.
Device Information(1)
PART NUMBER |
PACKAGE |
BODY SIZE (NOM) |
CDCE937, CDCEL937 |
TSSOP (20) |
6.50 mm x 4.40 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
4 Revision History
Changes from F Revision (March 2010) to G Revision
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Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
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Changed ApplicationsGo
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Changed Thermal Resistance Junction to Ambient, RθJA, values in Thermal Information From: 89 (0 lfm), 75 (150 lfm), 74 (200 lfm), 74 (250 lfm), and 69 (500 lfm) To: 89.04Go
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Deleted Input Capacitance figureGo
Changes from E Revision (October 2009) to F Revision
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Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, and PLL3 Configure Register TableGo
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Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4Go
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Changed under Example, fifth row, N", 2 places TO N'Go
Changes from D Revision (September 2009) to E Revision
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Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more information.Go
Changes from C Revision (January 2009) to D Revision
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Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions tableGo
Changes from B Revision (December 2007) to C Revision
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Changed Generic Configuration Register table SLAVE_ADR default value From: 00b To: 01bGo
Changes from A Revision (September 2007) to B Revision
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Changed Terminal Functions Table - the pin numbers to correspond with pin outs on the packageGo
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Changed Generic Configuration Register table RID default From: 0h To: XbGo
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Added note to PWDN description to Generic Configuration Register tableGo
Changes from * Revision (August 2007) to A Revision
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Changed the data sheet status From: Product Preview To: Production dataGo