SLPS430A August   2013  – August 2014 CSD95375Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
  7. 7 Electrical Characteristics
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Powering CSD95375Q4M And Gate Drivers
    3. 9.3 Undervoltage Lockout Protection (UVLO)
    4. 9.4 PWM Pin
    5. 9.5 SKIP# Pin
      1. 9.5.1 Zero Crossing (ZX) Operation
    6. 9.6 Integrated Boost-Switch
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Loss Curves
      2. 10.1.2 Safe Operating Curves (SOA)
      3. 10.1.3 Normalized Curves
      4. 10.1.4 Calculating Power Loss and SOA
        1. 10.1.4.1 Design Example
        2. 10.1.4.2 Calculating Power Loss
        3. 10.1.4.3 Calculating SOA Adjustments
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Recommended PCB Design Overview
      2. 11.1.2 Electrical Performance
      3. 11.1.3 Thermal Performance
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Recommended PCB Land Pattern
    3. 13.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration

PinOut_DPC-8_SLPS382_P2.gifFigure 1. Top View

Pin Description

PIN DESCRIPTION
NO. NAME
1 SKIP# This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the Sync FET. When SKIP# is High, the CSD95375Q4M operates in Forced Continuous Conduction Mode. A tri-state voltage on SKIP# puts the driver into a very low power state.
2 VDD Supply Voltage to Gate Drivers and internal circuitry.
3 PGND Power Ground, Needs to be connected to Pin 9 and PCB
4 VSW Voltage Switching Node – pin connection to the output inductor.
5 VIN Input Voltage Pin. Connect input capacitors close to this pin.
6 BOOT_R Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic cap from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. Boot_R is internally connected to VSW.
7 BOOT
8 PWM Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if greater than the Tri-State Shutdown Hold-off Time (t3HT)
9 PGND Power Ground