SNAS265J June 2005 – September 2015 DAC121S101 , DAC121S101-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description continued
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- DDC|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8 Detailed Description
8.1 Overview
The DAC121S101 device is a full-featured, general purpose 12-bit voltage-output digital-to-analog converter (DAC) with 10-µs settling time. Control of the output of the DAC is achieved over a 3-wire SPI interface. Once the DAC output has been set, additional communication with the DAC is not required unless the output condition needs to be changed. Likewise, the DAC121S101 power on state is 0 V. The DAC output will remain at 0 V until a valid write sequence is made.
A unique benefit of the DAC121S101 is the logic levels of the SPI™ input pins. The logic levels of SCLK, DIN, and SYNCB are independent of VA. As a result, the DAC121S101 can operate at a supply voltage (VA) that is higher than the microcontroller that is controlling the DAC. This feature is advantageous in applications where the analog circuitry is being run at 5 V in order to maximize signal-to-noise ratio and digital logic is running at 3 V in order to conserve power.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 DAC Section
The DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding is straight binary with an ideal output voltage of:
where
- D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 4095.
8.3.2 Resistor String
The resistor string is shown in Figure 34. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that the DAC is monotonic.
Figure 34. DAC Resistor String
8.3.3 Output Amplifier
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0 V to VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the amplifier are described in the Electrical Characteristics.
8.4 Device Functional Modes
8.4.1 Power-On Reset
The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC register is filled with zeros and the output voltage is 0 V and remains there until a valid write sequence is made to the DAC.
8.4.2 Power-Down Modes
The DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the control register.
Table 1. Modes of Operation
| DB13 | DB12 | OPERATING MODE |
|---|---|---|
| 0 | 0 | Normal Operation |
| 0 | 1 | Power-Down with 1kΩ to GND |
| 1 | 0 | Power-Down with 100kΩ to GND |
| 1 | 1 | Power-Down with Hi-Z |
When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of these bits the supply current drops to its power-down level and the output is pulled down with either a 1-kΩ or a 100-KΩ resistor, or is in a high-impedance state, as described in Table 1.
The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC register are unaffected when in power-down, so when coming out of power down the output voltage returns to the same voltage it was before entering power down. Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. The time to exit power-down (Wake-Up Time) is typically tWU µsec as stated in the A.C. and Timing Characteristics Table.
8.5 Programming
8.5.1 Serial Interface
The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing Diagram for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can initiate the next write cycle.
Since the SYNC and DIN buffers draw more current when they are high, they must be idled low between write sequences to minimize power consumption.
8.5.2 Input Shift Register
The input shift register, , has sixteen bits. The first two bits are don't cares and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 2.
Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the output voltage.