SLAS693C March   2010  – March  2015 DAC3283

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics - DC Specifications
    6. 7.6 Electrical Characteristics - AC Specifications
    7. 7.7 Electrical Characteristics - Digital Specifications
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Definition Of Specifications
        1. 8.3.1.1  Adjacent Carrier Leakage Ratio (ACLR)
        2. 8.3.1.2  Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR)
        3. 8.3.1.3  Differential Nonlinearity (DNL)
        4. 8.3.1.4  Gain Drift
        5. 8.3.1.5  Gain Error
        6. 8.3.1.6  Integral Nonlinearity (INL)
        7. 8.3.1.7  Intermodulation Distortion (IMD3, IMD)
        8. 8.3.1.8  Offset Drift
        9. 8.3.1.9  Offset Error
        10. 8.3.1.10 Output Compliance Range
        11. 8.3.1.11 Reference Voltage Drift
        12. 8.3.1.12 Spurious Free Dynamic Range (SFDR)
        13. 8.3.1.13 Noise Spectral Density (NSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1  Serial Interface
      2. 8.4.2  Data Interface
      3. 8.4.3  Input FIFO
      4. 8.4.4  FIFO Alarms
      5. 8.4.5  FIFO Modes of Operation
        1. 8.4.5.1 Dual Sync Souces Mode
        2. 8.4.5.2 Single Sync Source Mode
        3. 8.4.5.3 Bypass Mode
      6. 8.4.6  Multi-Device Operation
        1. 8.4.6.1 Multi-Device Synchronization: Dual Sync Sources Mode
        2. 8.4.6.2 Multi-Device Operation: Single Sync Source Mode
      7. 8.4.7  Data Pattern Checker
      8. 8.4.8  DATACLK Monitor
      9. 8.4.9  FIR Filters
      10. 8.4.10 Coarse Mixer
      11. 8.4.11 Quadrature Modulation Correction (QMC)
      12. 8.4.12 Digital Offset Control
      13. 8.4.13 Temperature Sensor
      14. 8.4.14 Sleep Modes
      15. 8.4.15 LVPECL Inputs
      16. 8.4.16 LVDS INPUTS
      17. 8.4.17 CMOS Digital Inputs
      18. 8.4.18 Reference Operation
      19. 8.4.19 DAC Transfer Function
      20. 8.4.20 Analog Current Outputs
      21. 8.4.21 Passive Interface to Analog Quadrature Modulators
    5. 8.5 Register Maps
      1. 8.5.1  CONFIG0 (address = 0x00) [reset = 0x70]
      2. 8.5.2  CONFIG1 (address = 0x01) [reset = 0x11]
      3. 8.5.3  CONFIG2 (address = 0x02) [reset = 0x00]
      4. 8.5.4  CONFIG3 (address = 0x03) [reset = 0x10]
      5. 8.5.5  CONFIG4 (address = 0x04) [reset = 0xFF]
      6. 8.5.6  CONFIG5 (address = 0x05) READ ONLY
      7. 8.5.7  CONFIG6 (address =0x06) [reset = 0x00]
      8. 8.5.8  CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)
      9. 8.5.9  CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)
      10. 8.5.10 CONFIG9 (address = 0x09) [reset = 0x7A]
      11. 8.5.11 CONFIG10 (address = 0x0A) [reset = 0xB6]
      12. 8.5.12 CONFIG11 (address = 0x0B) [reset = 0xEA]
      13. 8.5.13 CONFIG12 (address =0x0C) [reset = 0x45]
      14. 8.5.14 CONFIG13 (address =0x0D) [reset = 0x1A]
      15. 8.5.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]
      16. 8.5.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]
      17. 8.5.17 CONFIG16 (address = 0x10) [reset = 0xV6]
      18. 8.5.18 CONFIG17 (address = 0x11) [reset = 0x24]
      19. 8.5.19 CONFIG18 (address = 0x12) [reset = 0x02]
      20. 8.5.20 CONFIG19 (address = 0x13) [reset = 0x00]
      21. 8.5.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)
      22. 8.5.22 CONFIG21 (address = 0x15) [reset = 0x00]
      23. 8.5.23 CONFIG22 (address = 0x16) [reset = 0x00]
      24. 8.5.24 CONFIG23 (address = 0x17) [reset = 0x00]
      25. 8.5.25 CONFIG24 (address = 0x18) [reset = 0x83]
      26. 8.5.26 CONFIG25 (address = 0x19) [reset = 0x00]
      27. 8.5.27 CONFIG26 (address = 0x1a) [reset = 0x00]
      28. 8.5.28 CONFIG27 (address =0x1b) [reset = 0x00] (CAUSES AUTOSYNC)
      29. 8.5.29 CONFIG28 (address = 0x1C) [reset = 0x00]
      30. 8.5.30 CONFIG29 (address = 0x1D) [reset = 0x00]
      31. 8.5.31 CONFIG30 (address = 0x1E) [reset = 0x24]
      32. 8.5.32 VERSION31 (address = 0x1F) [reset = 0x12] (PARTIAL READ ONLY)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Direct Conversion Radio
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
    1. 10.1 Power-up Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power-up Sequence

The following startup sequence is recommended to power-up the DAC3283:

  1. Set TXENABLE low.
  2. Supply all 1.8V voltages (DACVDD, DIGVDD, CLKVDD and VFUSE) and all 3.3V voltages (AVDD). The 1.8V and 3.3V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.
  3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after the SIF register programming.
  4. Program all the SIF registers. Also program default value to the registers not being used.
  5. FIFO configuration needed for synchronization:
    1. Program fifo_reset_ena (config0, bit<5>) to enable FRAMEP/N as the FIFO input pointer sync source.
    2. Program multi_sync_ena (config0, bit<4>) to enable syncing of the FIFO output pointer.
    3. Program multi_sync_sel (config19, bit<1>) to select the FIFO output pointer and clock divider sync source
  6. Clock divider configuration needed for synchronization:
    1. Program clkdiv_sync_ena(config18, bit<1>) to "1" to enable clock divider sync.
  7. Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N, and FRAMEP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
    1. For Single Sync Source Mode where FRAMEP/N is used to sync the FIFO, a single rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
    2. For Dual Sync Sources Mode, either single pulse or periodic sync signals can be used.
  8. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization:
    1. For Single Sync Source Mode where the clock divider sync source is FRAMEP/N, clock divider syncing may be disabled after DAC3283 initialization and before the data transmission by setting clkdiv_sync_ena (config18, bit<1>) to “0”. This is to prevent accidental syncing of the clock divider when sending FRAMEP/N pulse to other digital blocks.
    2. For Dual Sync Sources Mode, where the clock divider sync source is from the OSTRP/N, the clock divider syncing may be enabled at all time.
    3. Optionally, to prevent accidental syncing of the FIFO, disable FIFO syncing by setting fifo_reset_ena and multi_sync_ena to "0" after the FIFO input and output pointers are initialized. If the FIFO sync remains enabled after initialization, the FRAMEP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail.
  9. Enable transmit of data by asserting the TXENABLE pin.
  10. At all times, if any of the clocks (i.e. DATACLK or DACCLK) is lost or FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat step 5 through 9. Program the FIFO configuration and clock divider configuration per step 5 and 6 appropriately to accept the new sync pulse or pulses for the synchronization.