SLASF07 September   2023 DAC43901-Q1 , DAC43902-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Comparator Mode
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast-Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
        2. 7.3.2.2 Power-Supply as Reference
        3. 7.3.2.3 Internal Reference
        4. 7.3.2.4 External Reference
      3. 7.3.3 Programming Interface
      4. 7.3.4 Nonvolatile Memory (NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.4.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.4.1.2 NVM-CRC-FAIL-INT Bit
      5. 7.3.5 Power-On Reset (POR)
      6. 7.3.6 External Reset
      7. 7.3.7 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
      2. 7.4.2 PWM Fade-In Fade-Out Mode
      3. 7.4.3 Sequential Turn-Indicator Animation Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Sequential Turn Indicator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Logarithmic Fade-In Fade-Out
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

PWM Fade-In Fade-Out Mode

The DAC43901-Q1 support a state-machine preconfigured for PWM (pulse-width-modulation) fade-in fade-out, used for smooth dimming of lights and starting of motors. The fade-in fade-out is done logarithmically. DAC channel 0 is used as a comparator and the TRIG-IN pin is used as the trigger input for the fade-in fade-out. The PWM outputs are available on the digital pins in standalone mode. The device goes into the standalone mode when the VREF/MODE pin is pulled high. In this mode, the programming interface is disabled. The digital programming interface (I2C and SPI) pins are open-drain outputs and must be pulled up to function as PWMx outputs. In standalone mode, the device runs using the configurations in NVM. Pulling the VREF/MODE pin low brings the device into programming mode. When the PWM output mode is enabled, all four programming interface pins act as PWMx outputs, even if not used. Partial selection is not possible. The fade-in fade-out PWM output is available on PWM0 (SDA/SCLK) and PWM1 (A0/SDI). Table 7-9 shows the PWM output mapping on the digital pins. The PWM duty-cycle resolution is 7 bits. The PWM0 transitions from the predefined minimum duty cycle to the maximum duty cycle on the rising edge of the trigger input and transitions from the maximum duty cycle to minimum duty cycle on the falling edge of the trigger input. The fade-in fade-out configurations for PWM0 are programmed using the SRAM or the register addresses shown in Table 7-10.

Table 7-3 Fade-In Fade-Out Pin Mapping
FADE-IN FADE-OUT INTERFACE MULTIPLEXED PROGRAMMING PIN PIN NO.
PWM0 SDA/SCLK 8
PWM1 A0/SDI 7
TRIG-IN TRIG-IN 1
GUID-20210506-CA0I-3MLZ-4NSR-LWLZRDVN1NG2-low.svg Figure 7-4 PWM Fade-In Fade-Out
GUID-20210506-CA0I-BXTL-WGBH-XBGFF3LWGSK9-low.svg Figure 7-5 Fade-In Fade-out High-Level Timing Diagram

By default the DAC43901-Q1 is configured in the PWM fade-in fade-out with the default settings as shown in Table 7-10. To change settings in the SRAM, write the SRAM address to the SRAM-ADDR register followed by a write to the SRAM-DATA register with the data. The register locations can be directly written with a single I2C or SPI sequence. In fade-in fade-out mode or animation mode, the basic setting is the fade-in or fade-out SLEW_RATE as depicted in Figure 7-6. The SLEW_RATE defines the timing resolution of the application. When the SLEW_RATE is multiplied with the number of steps in the fading, the fading time is obtained. The SLEW_RATE can be calculated using Equation 4. In logarithmic fading, the number of steps are nonlinear and also depend on the start and end duty-cycle settings. The total fading time is calculated using Equation 5 and Table 7-5. The fade-in can be started after a delay, calculated per Equation 7. CH0-DELAY defines the fade-in delay for PWM0, and COM-DELAY defines the fade-in delay for PWM1. The delay applies even when the fade-in is disabled by writing 0 for FADE-IN SLEW_RATE. In this case, a predefined delay setting of 256 is considered. There is no delay for fade-out.

GUID-20210620-CA0I-SMJC-MBKK-DRRC1SBF5VRK-low.svg Figure 7-6 Fade-in Fade-Out Detailed Timing Diagram
Equation 4. t S L E W ( μ s ) = 2.4 × S L E W _ R A T E + 5.6

where:

  • tSLEW_RATE is the fade-in or fade-out unit time in microseconds/step.
  • SLEW_RATE is the FADE-IN SLEW-RATE or FADE-OUT SLEW-RATE as specified in Table 7-10.

The pseudocode to compute the fade-in and fade-out steps is as follows:

min_duty = <user input>
max_duty = <use input>
if(min_duty == 0)
  min_duty = 1
#IF FADE-IN
current_duty = min_duty << 5
next_duty = integer(current_duty + (current_duty >> 5))
#ELIF FADE-OUT
current_duty = max_duty << 5
next_duty = integer(current_duty - (current_duty >> 5))
#ENDIF
current_duty = next_duty
output_duty = integer(next_duty >> 5)
#IF FADE-IN
if(output_duty > max_duty)
  output = max_duty
else
  output = output_duty
#ELIF FADE-OUT
if(output_duty < min_duty)
  output = min_duty
else
  output = output_duty
#ENDIF
Equation 5. t F A D E = t S L E W _ R A T E × n = P W M S T A R T P W M E N D R E P E T A T I O N ( n )

where:

  • tFADE is the total fading (fade-in or fade-out) time as depicted in Figure 7-6.
  • tSLEW_RATE is the fade-in or fade-out time slice in seconds/step.
  • SLEW_RATE is the FADE-IN SLRE-RATE or FADE-OUT SLEW-RATE, as specified in Table 7-10.
  • n is the CODE corresponding to the PWM duty cycle, as specified in Table 7-5.
  • PWMSTART is the PWM-MIN value for fade-in and PWM-MAX value for fade-out, as specified in Table 7-10.
  • PWMEND is the PWM-MAX value for fade-in and PWM-MIN value for fade-out, as specified in Table 7-10.
  • REPETATION(n) is the REPETITION(CODE) value specified for every PWM code, as specified in Table 7-5.

Table 7-11 shows the list of register settings done for the device configuration.

Table 7-4 Fade-In Fade-Out Configuration
REGISTER FIELD NAME LOCATION ADDRESS [BITS] DEFAULT VALUE DESCRIPTION
PWM-MAX SRAM, NVM 0x21 [6:0] 0xF7 Maximum PWM duty cycle
PWM-MIN SRAM, NVM 0x20 [6:0] 0x00 Minimum PWM duty cycle
FADE-IN SLEW-RATE SRAM, NVM 0x23 [15:0] 0x0000 See Equation 4 and Equation 5
FADE-OUT SLEW-RATE SRAM, NVM 0x26 [15:0] 0x0000 See Equation 4 and Equation 5
CH0-DELAY SRAM, NVM 0x24 [15:0] 0x0000 Delay for PWM0. See Equation 7
COM-DELAY SRAM, NVM 0x25 [15:0] 0x0000 Delay for PWM1. See Equation 7
PWM-FREQ SRAM, NVM 0x22 [11:7] 0x00 Frequency selection as per Table 7-7
Table 7-5 Fade-In Steps
CODE REPETATION (CODE) CODE REPETATION (CODE) CODE REPETATION (CODE) CODE REPETATION (CODE) CODE REPETATION (CODE)
1 32 17 2 33 1 54 1 88 1
2 16 18 2 34 1 55 1 90 1
3 11 19 2 35 1 57 1 93 1
4 8 20 1 36 1 59 1 96 1
5 7 21 2 37 1 61 1 99 1
6 5 22 1 38 1 62 1 102 1
7 5 23 2 39 1 64 1 105 1
8 4 24 1 41 1 66 1 109 1
9 3 25 1 42 1 68 1 112 1
10 4 26 2 43 1 71 1 116 1
11 3 27 1 45 1 73 1 119 1
12 2 28 1 46 1 75 1 123 1
13 3 29 1 47 1 77 1 127 1
14 2 30 1 49 1 80 1
15 2 31 1 50 1 82 1
16 2 32 1 52 1 85 1
Table 7-6 DAC43901-Q1 Register Settings
REGISTER NAME ADDRESS DEFAULT VALUE
COMMON-CONFIG 0x1F 0x13FF
DAC-0-VOUT-CMP-CONFIG 0x15 0x0407
STATE-MACHINE-CONFIG0 0x27 0x0003
Table 7-7 PWM Frequency Configuration
SRAM LOCATION PWM-FREQ PWM FREQUENCY (kHz) DUTY CYCLE (%) FOR CODE 1 DUTY CYCLE (%) FOR CODE 126
PWM-FREQ
(0x22 [11:7])
0 Invalid N/A N/A
1 48.828 4.88 95.12
2 24.414 2.44 97.56
3 16.276 1.63 98.37
4 12.207 1.22 98.44
5 8.138 0.81 98.44
6 6.104 0.78 98.44
7 3.052 0.78 98.44
8 2.035 0.78 98.44
9 1.526 0.78 98.44
10 1.221 0.78 98.44
11 1.017 0.78 98.44
12 0.872 0.78 98.44
13 0.763 0.78 98.44
14 0.678 0.78 98.44
15 0.610 0.78 98.44
16 0.555 0.78 98.44
17 0.509 0.78 98.44
18 0.470 0.78 98.44
19 0.436 0.78 98.44
20 0.407 0.78 98.44
21 0.381 0.78 98.44
22 0.359 0.78 98.44
23 0.339 0.78 98.44
24 0.321 0.78 98.44
25 0.305 0.78 98.44
26 0.291 0.78 98.44
27 0.277 0.78 98.44
28 0.265 0.78 98.44
29 0.254 0.78 98.44
30 0.244 0.78 98.44
31 0.218 0.78 98.44

The duty cycle of the PWM is proportional to the 7-bit code, 0d to 126d. As Table 7-8 shows, the code 127d corresponds to 100% duty cycle. The duty cycle 99.22% (127d/128d) is skipped to achieve 100% duty cycle using a 7-bit code. The PWM duty-cycle setting is done by the state machine and is not exposed to the user.

Table 7-8 PWM Duty Cycle Setting
CODE DUTY CYCLE DESCRIPTION
0 0% Always 0
1 0.78% Minimum linear duty cycle
x (x/128)% x is the code between 2d and 125d, both included
126 98.44% Maximum linear duty cycle
127 100% Always 1. The duty cycle 99.22% (127d/128d) is skipped.