SBAS794C November   2018  – November 2019 DAC60501 , DAC70501 , DAC80501

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      Offset Trimming With the DACx0501
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements : SPI Mode
    7. 7.7  Timing Requirements : I2C Standard Mode
    8. 7.8  Timing Requirements : I2C Fast Mode
    9. 7.9  Timing Requirements : I2C Fast-Mode Plus
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 DACx0501 I2C Update Sequence
            1. 8.5.1.2.2.1 DACx0501 Address Byte
            2. 8.5.1.2.2.2 DACx0501 Command Byte
            3. 8.5.1.2.2.3 DACx0501 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 DACx0501 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1 NOOP Register (offset = 0h) [reset = 0000h]
        1. Table 8. NOOP Register Field Descriptions
      2. 8.6.2 DEVID Register (offset = 1h)
        1. Table 9. DEVID Register Field Descriptions
      3. 8.6.3 SYNC Register (offset = 2h) [reset = 0000h]
        1. Table 10. SYNC Register Field Descriptions
      4. 8.6.4 CONFIG Register (offset = 3h) [reset = 0000h]
        1. Table 11. CONFIG Register Field Descriptions
      5. 8.6.5 GAIN Register (offset = 4h) [reset = 0001h]
        1. Table 12. GAIN Register Field Descriptions
      6. 8.6.6 TRIGGER Register (offset = 5h) [reset = 0000h]
        1. Table 13. TRIGGER Register Field Descriptions
      7. 8.6.7 STATUS Register (offset = 7h) [reset = 0000h]
        1. Table 14. STATUS Register Field Descriptions
      8. 8.6.8 DAC Register (offset = 8h) [reset = 0000h for DACx0501Z or reset = 8000h for DACx0501M]
        1. Table 15. DAC Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Charge Injection
        2. 9.2.2.2 Voltage Droop
        3. 9.2.2.3 Output Offset Error
        4. 9.2.2.4 Switch Selection
        5. 9.2.2.5 Amplifier Selection
        6. 9.2.2.6 Hold Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 16-bit performance: 1-LSB INL and DNL (max)
  • Low glitch energy: 4 nV–s
  • Wide power supply: 2.7 V to 5.5 V
  • Buffered output range: 5 V, 2.5 V, or 1.25 V
  • Very-low power: 1 mA at 5.5 V
  • Integrated 5-ppm/˚C (max), 2.5-V precision reference
  • Pin-selectable serial interface:
    • 3-wire, SPI compatible up to 50-MHz
    • 2-wire, I2C compatible
  • Power-on-reset: Zero scale or midscale
  • 1.62-V VIH with VDD = 5.5 V
  • Temperature range: –40˚C to +125˚C
  • Packages: Small 8-Pin WSON and 10-Pin VSSOP