SBAS368D May   2006  – December 2016 DDC264

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dual Switched Integrator: Basic Integration Cycle
      2. 8.3.2 Integration Capacitors
      3. 8.3.3 Voltage Reference
      4. 8.3.4 Serial Data Output and Control Interface
        1. 8.3.4.1 System and Data Clocks (CLK and DCLK)
        2. 8.3.4.2 CONV: Setting the Integration Time
        3. 8.3.4.3 Data Valid (DVALID)
        4. 8.3.4.4 Data Format
        5. 8.3.4.5 Data Retrieval
          1. 8.3.4.5.1 Cascading Multiple Converters
          2. 8.3.4.5.2 Retrieval Before CONV Toggles
          3. 8.3.4.5.3 Retrieval After CONV Toggles
          4. 8.3.4.5.4 Retrieval Before and After CONV Toggles
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Reset (RESET)
      2. 8.5.2 Configuration Register — Read and Write Operations
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Connection
        2. 9.2.2.2 Selecting Integration Time, Device Clock, and Range
        3. 9.2.2.3 Voltage Reference
        4. 9.2.2.4 Reading the Measurement
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequencing
    2. 10.2 Power Supplies and Grounding
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Shielding Analog Signal Paths
      2. 11.1.2 Power Supply Routing
      3. 11.1.3 Reference Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power-Up Sequencing

Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals must remain low until the power supplies have stabilized, as shown in Figure 34. The analog supply must come up before or at the same time as the digital supply. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then give a RESET pulse. After releasing RESET, the Configuration Register must be written. Table 11 shows the timing for the power-up sequence.

DDC264 ai_tim_pwrup_bas368.gif Figure 34. DDC264 Timing Diagram at Power-Up

Table 11. Timing for DDC264 Power-Up Sequence

MIN TYP MAX UNIT
tPOR Wait after power-up until reset 250 ms

10.2 Power Supplies and Grounding

Both AVDD and DVDD must be as quiet as possible. It is particularly important to eliminate noise from AVDD that is non-synchronous with the DDC264 operation. Figure 35 illustrates how to supply power to the DDC264. Each DDC264 has internal bypass capacitors on AVDD and DVDD; therefore, the only external bypass capacitors typically required are 10-µF ceramic capacitors, one per PCB. TI recommends connecting both the analog and digital grounds (AGND and DGND) to a single ground plane on the PCB.

DDC264 pwr_connex_SBAS368.gif Figure 35. Power Supply Connections