DLPS173B august   2020  – july 2023 DLP471TP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  10. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER (1)(2)TEST CONDITIONS (1)MINTYPMAXUNIT
CURRENT – TYPICAL
IDDSupply current VDD(3)8001200mA
IDDASupply current VDDA(3)10001200mA
IOFFSETSupply current VOFFSET(4)(5)2025mA
IBIASSupply current VBIAS(4)(5)2.54.0mA
IRESETSupply current VRESET(5)-9.3-6.9mA
POWER – TYPICAL
PDDSupply power dissipation VDD(3)14402437.5mW
PDDASupply power dissipation VDDA(3)16202340mW
POFFSETSupply power dissipation VOFFSET(4)(5)230367.5mW
PBIASSupply power dissipation VBIAS(4)(5)43.270.3mW
PRESETSupply power dissipation VRESET(5)107.8152.25mW
PTOTALSupply power dissipation Total34415367.55mW
LVCMOS INPUT
IILLow level input current (6)VDD = 1.95 V, VI = 0 V–100nA
IIHHigh level input current (6)VDD = 1.95 V, VI = 1.95 V135uA
LVCMOS OUTPUT
VOHDC output high voltage (7)IOH = -2 mA0.8 x VDDV
VOLDC output low voltage (7)IOL = 2 mA0.2 x VDDV
RECEIVER EYE CHARACTERISTICS
A1Minimum data eye opening (8)(9)100400600mV
A2Maximum data signal swing (8)(9)600mV
X1Maximum data eye closure (8)0.275UI
X2Maximum data eye closure (8)0.4UI
| tDRIFT |Drift between Clock and Data between Training Patterns20ps
CAPACITANCE
CINInput capacitance LVCMOSf = 1 MHz10pF
CINInput capacitance LSIF (low speed interface)f = 1 MHz20pF
CINInput capacitance HSSI (high speed serial interface)f = 1 MHz20pF
COUTOutput capacitancef = 1 MHz10pF
All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are required to operate the DMD.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
Refer to Figure 6-11, Receiver Eye Mask (1e-12 BER).