DLPS153 October   2023 DLP651LE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Optical Interface and System Image Quality Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 Micromirror Array Temperature Calculation
    6. 7.6 Micromirror Power Density Calculation
    7. 7.7 Window Aperture Illumination Overfill Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
  11. 10Power Supply Recommendations
    1. 10.1 DMD Power Supply Power-Up Procedure
    2. 10.2 DMD Power Supply Power-Down Procedure
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • FYM|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2 DMD Power Supply Power-Down Procedure

  • During power-down, VCC and VCCI must be supplied until after VCC2 is discharged to within the specified limit of ground. Refer to Section 6.4.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1 and Section 6.4.
  • During power-down, LVCMOS input pins must be less than specified in Section 6.4.
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A. See Pin Configuration and Functions for pin functions.
B. VCC must be up and stable prior to VCC2 powering up.
C. PWRDNZ has two turn on options. Option 1: PWRDNZ does not go high until VCC and VCC2 are up and stable, or Option 2: PWRDNZ must be pulsed low for a minimum of TPWRDNZ, or 10 ns after VCC and VCC2 are up and stable.
D. There is a minimum of TLVDS_ARSTZ, or 2 μs, wait time from PWRDNZ going high for the LVDS receiver to recover.
E. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates the PWRDNZ and disables VCC2.
F. Under power-loss conditions, where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, PWRDNZ goes low.
G. VCC must remain high until after VCC2 goes low.
H. To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit in Section 6.4.
Figure 10-1 Power Supply Timing(1)