DLPS084D January   2017  – August 2021 DLPC3437

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 Parallel Interface Data Transfer Format
      2. 7.3.2 Device Start-Up
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast PARK Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.3.9.1 Sub-LVDS (HS) Interface

Table 7-8 shows how the 8 sub-LVDS lanes are configured for the DLP3310 (.33 1080p) DMD.

Table 7-8 DLP3310 (.33 1080p) DMD – DLPC to 8-Lane DMD Pin Mapping
DLPC3437 8 LANE DMD ROUTING OPTION #1
PRIMARY DLPC3437 PINS
 SECONDARY DLPC3437 PINS
 DMD PINS
HS_WDATA_D_P
HS_WDATA_D_N		 HS_WDATA_E_P
HS_WDATA_E_N		 Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N		 HS_WDATA_F_P
HS_WDATA_F_N		 Input DATA_p_1
Input DATA_n_1
HS_WDATA_B_P
HS_WDATA_B_N		 HS_WDATA_G_P
HS_WDATA_G_N		 Input DATA_p_2
Input DATA_n_2
HS_WDATA_A_P
HS_WDATA_A_N		 HS_WDATA_H_P
HS_WDATA_H_N		 Input DATA_p_3
Input DATA_n_3
HS_WDATA_H_P
HS_WDATA_H_N		 HS_WDATA_A_P
HS_WDATA_A_N		 Input DATA_p_4
Input DATA_n_4
HS_WDATA_G_P
HS_WDATA_G_N		 HS_WDATA_B_P
HS_WDATA_B_N		 Input DATA_p_5
Input DATA_n_5
HS_WDATA_F_P
HS_WDATA_F_N		 HS_WDATA_C_P
HS_WDATA_C_N		 Input DATA_p_6
Input DATA_n_6
HS_WDATA_E_P
HS_WDATA_E_N		 HS_WDATA_D_P
HS_WDATA_D_N		 Input DATA_p_7
Input DATA_n_7
DLPC3437 8 LANE DMD ROUTING OPTION #2
PRIMARY DLPC3437 PINS
 SECONDARY DLPC3437 PINS
 DMD PINS
HS_WDATA_E_P
HS_WDATA_E_N		 HS_WDATA_D_P
HS_WDATA_D_N		 Input DATA_p_0
Input DATA_n_0
HS_WDATA_F_P
HS_WDATA_F_N		 HS_WDATA_C_P
HS_WDATA_C_N		 Input DATA_p_1
Input DATA_n_1
HS_WDATA_G_P
HS_WDATA_G_N		 HS_WDATA_B_P
HS_WDATA_B_N		 Input DATA_p_2
Input DATA_n_2
HS_WDATA_H_P
HS_WDATA_H_N		 HS_WDATA_A_P
HS_WDATA_A_N		 Input DATA_p_3
Input DATA_n_3
HS_WDATA_A_P
HS_WDATA_A_N		 HS_WDATA_H_P
HS_WDATA_H_N		 Input DATA_p_4
Input DATA_n_4
HS_WDATA_B_P
HS_WDATA_B_N		 HS_WDATA_G_P
HS_WDATA_G_N		 Input DATA_p_5
Input DATA_n_5
HS_WDATA_C_P
HS_WDATA_C_N		 HS_WDATA_F_P
HS_WDATA_F_N		 Input DATA_p_6
Input DATA_n_6
HS_WDATA_D_P
HS_WDATA_D_N		 HS_WDATA_E_P
HS_WDATA_E_N		 Input DATA_p_7
Input DATA_n_7
Figure 7-12 DLP3310 (.33 1080p) DMD Interface Example (Option 1 and 2)

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.