SLVSBH2C June   2012  – December 2015 DRV8823-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Protection Circuits
        1. 7.3.2.1 Overcurrent Protection (OCP)
        2. 7.3.2.2 Thermal Shutdown (TSD)
        3. 7.3.2.3 Undervoltage Lockout (UVLO)
        4. 7.3.2.4 Shoot-Through Current Prevention
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
      2. 7.4.2 Current Regulation
      3. 7.4.3 Decay Mode
      4. 7.4.4 Blanking Time
    5. 7.5 ProgrammingData Format to Programming
      1. 7.5.1 Serial Data Transmission
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DRV8823-Q1 is a dual stepper motor driver solution for automotive applications that require independent control of two different motors. The device integrates four NMOS H-bridges, a microstepping indexer, and various fault protection features. The DRV8823-Q1 can be powered with a supply voltage between 8 V and 32 V, and is capable of providing an output current up to 1.5-A full scale. Actual full-scale current will depend on ambient temperature, supply voltage and PCB ground size.

A serial data interface is included to control all functions of the motor driver. Current regulation through all four H-bridges is achieved using three register bits per H-bridge. The three register bits are used to scale the current in each bridge as a percentage of the full-scale current set by VREF input pin and sense resistor. The current regulation is configurable with two different decay modes; slow decay and mixed decay.

The gate drive to each FET in all four H-Bridges is controlled to prevent any cross-conduction (shoot-through current) during transitions.

7.2 Functional Block Diagram

DRV8823-Q1 blk_diag1_lvs913.gif

7.3 Feature Description

7.3.1 PWM Motor Drivers

The DRV8823-Q1 device contains four H-bridge motor drivers with current-control PWM circuitry. A block diagram showing drivers A and B of the motor control circuitry (as typically used to drive a bipolar stepper motor) is shown in Figure 11. Drivers C and D are the same as A and B (though the RDS(ON) of the output FETs is different).

DRV8823-Q1 driver_blk_diag_lvs913.gif Figure 11. Motor Driver Circuit

Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage.

7.3.2 Protection Circuits

The DRV8823-Q1 device is fully protected against undervoltage, overcurrent, and overtemperature events.

7.3.2.1 Overcurrent Protection (OCP)

All of the drivers in the DRV8823-Q1 device are protected with an overcurrent protection (OCP) circuit.

The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each output FET if the current through it exceeds a preset level. This circuit limits the current to a level that is safe to prevent damage to the FET.

A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than a preset period, all drivers in the device are disabled.

The device is re-enabled upon the removal and re-application of power at the VM pins.

7.3.2.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all drivers in the device are shut down.

The device remains disabled until the die temperature falls to a safe level. After the temperature falls, the device may be re-enabled upon the removal and re-application of power at the VM pin.

7.3.2.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device is disabled. Operation resumes when VM rises above the UVLO threshold. The indexer logic is reset to its initial condition in the event of a UVLO.

7.3.2.4 Shoot-Through Current Prevention

The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot-through current) during transitions.

7.4 Device Functional Modes

7.4.1 Bridge Control

The xENBL bits in the serial interface registers enable current flow in each H-bridge when set to 1.

The xPHASE bits in the serial interface registers control the direction of current flow through each H-bridge. Table 1 shows the logic.

Table 1. H-Bridge Logic

xPHASE xOUT1 xOUT2
1 H L
0 L H

7.4.2 Current Regulation

The motor driver employs fixed-frequency PWM current regulation (also called current chopping). When a winding is activated, the current through it rises until it reaches a threshold, then the current is switched off until the next PWM period.

The PWM frequency is fixed at 50 kHz, but it may also be set to 100 kHz through the factory option.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the VREF pin.

The full-scale (100%) chopping current is calculated as follows:

Equation 1. DRV8823-Q1 equat1_lvs912.gif

Example:

If a 0.5-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current is:
2.5 V/(5 × 0.5 Ω) = 1 A.

Three serial interface register bits per H-bridge (xI2, xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The function of the bits is shown in Table 2.

Table 2. H-Bridge Bit Functions

xI2 xI1 xI0 RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
0 0 0 20
0 0 1 38
0 1 0 56
0 1 1 71
1 0 0 83
1 0 1 92
1 1 0 98
1 1 1 100

7.4.3 Decay Mode

During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 12 as case 1. The current flow direction shown indicates positive current flow in Figure 12.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 12 as case 2.

In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is shown in Figure 12 as case 3.

DRV8823-Q1 drv8811_decay_lvs865.gif Figure 12. Decay Mode

The DRV8823-Q1 device supports slow decay and a mixed decay mode. Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period.

Slow or mixed decay mode is selected by the state of the xDECAY bits in the serial interface registers. If the xDECAY bit is 0, slow decay is selected. If the xDECAY bit is 1, mixed decay is selected.

7.4.4 Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also sets the minimum on time of the PWM.

7.5 Programming

7.5.1 Serial Data Transmission

Data transfers consist of 16 bits of serial data, shifted into the SDATA pin LSB first.

On serial writes to the DRV8823-Q1 device, additional clock edges following the final data bit continues to shift data bits into the data register; therefore, the last 16 bits presented are latched and used.

One of two registers is selected by setting bits in an address field in the four upper bits in the serial data transferred (ADDR in the tables below). One 16-bit register is used to control motor number 1 (bridges A and B), and a second 16-bit register is used to control motor 2 (bridges C and D).

Data can only be transferred into the serial interface if the SCS input pin is active high.

Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the rising edge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits have been transferred.

Table 3. Motor 1 Command (Bridges A and B)

Bit D15–
D12		 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name ADDR
(= 0000)		 BDECAY B12 B11 B10 BPHASE BENBL ADECAY A12 A11 A10 APHASE AENBL
Reset Value x 0 0 0 0 0 0 0 0 0 0 0 0

Table 4. Motor 2 Command (Bridges C and D)

Bit D15–
D12		 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name ADDR
(= 0001)		 DDECAY D12 D11 D10 DPHASE DENBL CDECAY C12 C11 C10 CPHASE CENBL
Reset Value x 0 0 0 0 0 0 0 0 0 0 0 0
DRV8823-Q1 ser_data_tmg_lvs913.gif
Note 1: Any amount of time is allowed between clocks, or groups of clocks, as long as SCS stays active. This allows 8- or 16-bit transfers.
Note 2: If more than 16 clock edges are presented while transferring data (while SCS is still high), data continues to be shifted into the data register.
Figure 13. Serial Data Timing Diagram