SNLS514C November   2015  – October 2019 DS280BR810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics -- Serial Management Bus Interface
    7. 6.7 Timing Requirements -- Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver and Transmitter
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documents
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.2 Global Registers: Channel Selection and ID Information

The global registers can be accessed at any time, regardless of whether the shared or channel register set is selected. The DS280BR810 global registers are located at address 0xEF - 0xFF.

Table 2. Global Register Map

Addr [HEX] Bit Default [HEX] Mode EEPROM Field Description
0xEF 0x0C General
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 1 R N DEVICE_ID_QUAD_CNT[3] TI device ID (quad count). Contains 0x0C.
2 1 R N DEVICE_ID_QUAD_CNT[2]
1 0 R N DEVICE_ID_QUAD_CNT[1]
0 0 R N DEVICE_ID_QUAD_CNT[0]
0xF0 0x00 Version Revision
7 0 R N TYPE TI version ID. Contains 0x00.
6 0 R N VERSION[6]
5 0 R N VERSION[5]
4 0 R N VERSION[4]
3 0 R N VERSION[3]
2 0 R N VERSION[2]
1 0 R N VERSION[1]
0 0 R N VERSION[0]
0xF1 0x40 Channel Control
7 0 R N DEVICE_ID[7] TI device ID. Contains 0x40.
6 1 R N DEVICE_ID[6]
5 0 R N DEVICE_ID[5]
4 0 R N DEVICE_ID[4]
3 0 R N DEVICE_ID[3]
2 0 R N DEVICE_ID[2]
1 0 R N DEVICE_ID[1]
0 0 R N DEVICE_ID[0]
0xF3 0x00 Channel Control
7 0 R N CHAN_VERSION[3] TI digital channel version ID. Contains 0x00.
6 0 R N CHAN_VERSION[2]
5 0 R N CHAN_VERSION[1]
4 0 R N CHAN_VERSION[0]
3 0 R N SHARE_VERSION[3] TI digital share version ID. Contains 0x00.
2 0 R N SHARE_VERSION[2]
1 0 R N SHARE_VERSION[1]
0 0 R N SHARE_VERSION[0]
0xFC 0x00 General
7 0 RW N EN_CH7 Select channel 7
6 0 RW N EN_CH6 Select channel 6
5 0 RW N EN_CH5 Select channel 5
4 0 RW N EN_CH4 Select channel 4
3 0 RW N EN_CH3 Select channel 3
2 0 RW N EN_CH2 Select channel 2
1 0 RW N EN_CH1 Select channel 1
0 0 RW N EN_CH0 Select channel 0
0xFD 0x00
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0xFE 0x03 Vendor ID
7 0 R N VENDOR_ID[7] TI vendor ID. Contains 0x03.
6 0 R N VENDOR_ID[6]
5 0 R N VENDOR_ID[5]
4 0 R N VENDOR_ID[4]
3 0 R N VENDOR_ID[3]
2 0 R N VENDOR_ID[2]
1 1 R N VENDOR_ID[1]
0 1 R N VENDOR_ID[0]
0xFF 0x10 Channel Control
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N EN_SHARE_Q1 Select shared registers for Quad 1 (Channels 4-7).
4 1 RW N EN_SHARE_Q0 Select shared registers for Quad 0 (Channels 0-3).
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N WRITE_ALL_CH Allows customer to write to all channels as if they are the same, but only allows to read back from the channel specified in 0xFC and 0xFD.
Note: EN_CH_SMB must be = 1 or else this function is invalid.
0 0 RW N EN_CH_SMB 1: Enables SMBus access to the channels specified in register 0xFC.
0: The shared registers are selected, see 0xFF[5:4].