SNLS703 December   2023 DS90LVRA2-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Decoupling Recommendations
        2. 8.2.2.2 Termination
        3. 8.2.2.3 Input Failsafe Biasing
        4. 8.2.2.4 Probing LVDS Transmission Lines
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Differential Traces
        2. 8.4.1.2 PC Board Considerations
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DEM|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VITH Differential input high threshold VIB = -4 V or 5V, VCC = 1.62 V to 3.6 V 100 mV
VITL Differential input low threshold -100
VHYS Differential input voltage hysteresis, VIT1 – VIT2 VCC = 1.62 V to 3.6 V 20 40 120 mV
VCM_RANGE Input common mode voltage range VCC = 1.62 - 1.98V -1 1.2 2 V
VCC = 2.3 - 2.7 V -2.5 1.2 3 V
VCC = 3.0 - 3.6 V -4 1.2 5 V
VOH High-level output voltage IOH = –4mA, VCC = 1.8V ± 10% 1.3 V
IOH = –4mA, VCC = 2.5V ± 10% 1.8 V
IOH = –4mA, VCC = 3.3V ± 10% 2.6 V
VOL Low-level output voltage IOL = 4mA, VCC = 1.8V ± 10% 0.2 V
IOL = 4mA, VCC = 2.5V ± 10% 0.3 V
IOL = 4mA, VCC = 3.3V ± 10% 0.4 V
ICC_ACTIVE Supply current VCC = 3.6 V, No load, Steady-state, VID=200mV/-200mV 25 mA
VCC = 2.7 V, No load, Steady-state, VID=200mV/-200mV 25 mA
VCC = 1.98V, No load, Steady-state, VID=200mV/-200mV 25 mA
II Input current
(A or B inputs)
VI = -1.0 V, Other input open ±35 µA
VI = 2.4 V, Other input open ±20 µA
VI = –4 V, Other input open (split between 85℃) (±80 μA) ±120 µA
VI = 5V, Other input open ±40 µA
II(OFF) Power-off output current
(Y or Z outputs)
Vor VZ = 1.98V, VCC = 0 V ±20 µA
II(OFF) Power-off input current
(A or B inputs)
VA or VB = -1 V or 2.0 V, VCC = 0 V ±30 µA
VA or VB = –4 or 5V, VCC = 0 V ±70 µA
VA or VB = 0 V or 2.4 V, VCC = 0 V ±30 µA