SNLS477B October 2014 – November 2018 DS90UB948-Q1
The input RGB data is split into odd and even pixels starting with the ODD (first) pixel outputs D0 to D3 and then the EVEN (second) pixel outputs D4 to D7. The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to HIGH indicating active data.
In this configuration the PCLK rate embedded within the 1-lane FPD-Link III frame can range from 50 MHz to 96 MHz, resulting in a link rate of 1.75 Gbps (35 bit × 50 MHz) to 3.36 Gbps (35 bit × 96 MHz). Each LVDS data lane operates at a speed of 7 bits per 2 LVDS clock cycles, resulting in a serial line rate of 175 Mbps to 336 Mbps. CLK1 and CLK2 operate at half the rate as PCLK with a duty cycle ratio of 57:43.