SNLS477D October   2014  – February 2022 DS90UB948-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
        1. 7.4.2.1 Dual Swap
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
        1. 7.5.3.1 LUT Programming Example
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Controller Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Controller Operation
      4. 7.6.4 Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Controller Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Controller Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.3 OpenLDI Output Frame and Color Bit Mapping Select

DS90UB948-Q1can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different mapping schemes, shown in Figure 7-18 and Figure 7-19. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from CLK1± and CLK2± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is controlled by MODE_SEL0 pin or by Register (Section 7.7).

Table 7-10 lists common industry standard naming conventions for these LVDS bit mapping schemes.

Table 7-10 LVDS Formats
24 Bit Mode 18 Bit Mode
MAPSEL = H OLDI/SPWG/VESA 4 Lane 18 Bit Mode
MAPSEL = L JEIDA Standard 18 bit

GUID-C68FDB0A-D424-4CD3-931C-E2F1F8FEB2A0-low.gif Figure 7-18 24-Bit Color Dual FPD-Link Mapping: MSBs on D3/D7,"OLDI/SPWG/VESA" (MAPSEL = H)
GUID-EE98D959-77C3-436E-869F-DB367B716F9C-low.gif Figure 7-19 24-Bit Color Dual FPD-Link Mapping: LSBs on D3/D7, "JEIDA" (MAPSEL = L)
GUID-744133C4-FA76-4F87-AE5B-5EFE5A48F2A2-low.gif Figure 7-20 24-Bit Color Single FPD-Link Mapping: MSBs on D3, "OLDI/SPWG/VESA" (MAPSEL = H)
GUID-44E9FF3A-4817-4157-874B-32417B13397C-low.gif Figure 7-21 24-Bit Color Single FPD-Link Mapping: LSBs on D3, "JEIDA" (MAPSEL = L)
GUID-1D82C10C-C4CC-42A1-AFE0-9DBE554F446A-low.gif Figure 7-22 18-Bit Color Dual FPD-Link Mapping, "4 Lane 18 Bit Mode" (MAPSEL = H)
GUID-4ED884C5-AA29-4A8E-AE4D-65BA395F3268-low.gif Figure 7-23 18-Bit Color Dual FPD-Link Mapping, Standard 18 Bit (MAPSEL = L)
GUID-96C17449-44D1-4939-86EF-6C4996E5EE7F-low.gif Figure 7-24 18-Bit Color Single FPD-Link Mapping, "4 Lane 18 Bit Mode" (MAPSEL = H)
GUID-80BEE2FA-F63B-4401-9CE9-1AB6320D2EAF-low.gif Figure 7-25 18-Bit Color Single FPD-Link Mapping, Standard 18 Bit (MAPSEL = L)