SNLS477B October 2014 – November 2018 DS90UB948-Q1
The AEQ circuit can be restarted at any time by setting the AEQ_RESTART bit in the AEQ_CTL1 register 0x35. Once the deserializer is powered on, the AEQ is continually searching through EQ settings and could be at any setting when signal is supplied from the serializer. If the Rx Port CDR locks to the signal, it may be good enough for low bit errors, but could be not optimized or over-equalized. For a consistent initial EQ setting, TI recommends that the user applies AEQ_RESTART or DIGITAL_RESET0 when the serializer input signal frequency is stable to restart adaption from the minimum EQ gain value.