SNLS477B October   2014  – November 2018 DS90UB948-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1. 3.1 Typical Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Master Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Master Operation
      4. 7.6.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Master Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
        1. 7.7.1.1  I2C_DEVICE_ID Register (Address = 0x0) [reset = STRAP]
          1. Table 12. I2C_DEVICE_ID Register Field Descriptions
        2. 7.7.1.2  RESET Register (Address = 0x1) [reset = 0x0]
          1. Table 13. RESET Register Field Descriptions
        3. 7.7.1.3  GENERAL_CONFIGURATION_0 Register (Address = 0x2) [reset = 0x0]
          1. Table 14. GENERAL_CONFIGURATION_0 Register Field Descriptions
        4. 7.7.1.4  GENERAL_CONFIGURATION_1 Register (Address = 0x3) [reset = 0x70]
          1. Table 15. GENERAL_CONFIGURATION_1 Register Field Descriptions
        5. 7.7.1.5  BCC_WATCHDOG_CONTROL Register (Address = 0x4) [reset = 0xFE]
          1. Table 16. BCC_WATCHDOG_CONTROL Register Field Descriptions
        6. 7.7.1.6  I2C_CONTROL_1 Register (Address = 0x5) [reset = 0x1E]
          1. Table 17. I2C_CONTROL_1 Register Field Descriptions
        7. 7.7.1.7  I2C_CONTROL_2 Register (Address = 0x6) [reset = 0x0]
          1. Table 18. I2C_CONTROL_2 Register Field Descriptions
        8. 7.7.1.8  REMOTE_ID Register (Address = 0x7) [reset = 0x0]
          1. Table 19. REMOTE_ID Register Field Descriptions
        9. 7.7.1.9  SLAVEID_0 Register (Address = 0x8) [reset = 0x0]
          1. Table 20. SLAVEID_0 Register Field Descriptions
        10. 7.7.1.10 SLAVEID_1 Register (Address = 0x9) [reset = 0x0]
          1. Table 21. SLAVEID_1 Register Field Descriptions
        11. 7.7.1.11 SLAVEID_2 Register (Address = 0xA) [reset = 0x0]
          1. Table 22. SLAVEID_2 Register Field Descriptions
        12. 7.7.1.12 SLAVEID_3 Register (Address = 0xB) [reset = 0x0]
          1. Table 23. SLAVEID_3 Register Field Descriptions
        13. 7.7.1.13 SLAVEID_4 Register (Address = 0xC) [reset = 0x0]
          1. Table 24. SLAVEID_4 Register Field Descriptions
        14. 7.7.1.14 SLAVEID_5 Register (Address = 0xD) [reset = 0x0]
          1. Table 25. SLAVEID_5 Register Field Descriptions
        15. 7.7.1.15 SLAVEID_6 Register (Address = 0xE) [reset = 0x0]
          1. Table 26. SLAVEID_6 Register Field Descriptions
        16. 7.7.1.16 SLAVEID_7 Register (Address = 0xF) [reset = 0x0]
          1. Table 27. SLAVEID_7 Register Field Descriptions
        17. 7.7.1.17 SLAVEALIAS_0 Register (Address = 0x10) [reset = 0x0]
          1. Table 28. SLAVEALIAS_0 Register Field Descriptions
        18. 7.7.1.18 SLAVEALIAS_1 Register (Address = 0x11) [reset = 0x0]
          1. Table 29. SLAVEALIAS_1 Register Field Descriptions
        19. 7.7.1.19 SLAVEALIAS_2 Register (Address = 0x12) [reset = 0x0]
          1. Table 30. SLAVEALIAS_2 Register Field Descriptions
        20. 7.7.1.20 SLAVEALIAS_3 Register (Address = 0x13) [reset = 0x0]
          1. Table 31. SLAVEALIAS_3 Register Field Descriptions
        21. 7.7.1.21 SLAVEALIAS_4 Register (Address = 0x14) [reset = 0x0]
          1. Table 32. SLAVEALIAS_4 Register Field Descriptions
        22. 7.7.1.22 SLAVEALIAS_5 Register (Address = 0x15) [reset = 0x0]
          1. Table 33. SLAVEALIAS_5 Register Field Descriptions
        23. 7.7.1.23 SLAVEALIAS_6 Register (Address = 0x16) [reset = 0x0]
          1. Table 34. SLAVEALIAS_6 Register Field Descriptions
        24. 7.7.1.24 SLAVEALIAS_7 Register (Address = 0x17) [reset = 0x0]
          1. Table 35. SLAVEALIAS_7 Register Field Descriptions
        25. 7.7.1.25 MAILBOX_18 Register (Address = 0x18) [reset = 0x0]
          1. Table 36. MAILBOX_18 Register Field Descriptions
        26. 7.7.1.26 MAILBOX_19 Register (Address = 0x19) [reset = 0x1]
          1. Table 37. MAILBOX_19 Register Field Descriptions
        27. 7.7.1.27 GPIO_9__and_GLOBAL_GPIO_CONFIG Register (Address = 0x1A) [reset = 0x0]
          1. Table 38. GPIO_9__and_GLOBAL_GPIO_CONFIG Register Field Descriptions
        28. 7.7.1.28 FREQUENCY_COUNTER Register (Address = 0x1B) [reset = 0x0]
          1. Table 39. FREQUENCY_COUNTER Register Field Descriptions
        29. 7.7.1.29 GENERAL_STATUS Register (Address = 0x1C) [reset = 0x0]
          1. Table 40. GENERAL_STATUS Register Field Descriptions
        30. 7.7.1.30 GPIO0_CONFIG Register (Address = 0x1D) [reset = 0x3]
          1. Table 41. GPIO0_CONFIG Register Field Descriptions
        31. 7.7.1.31 GPIO1_2_CONFIG Register (Address = 0x1E) [reset = 0x3]
          1. Table 42. GPIO1_2_CONFIG Register Field Descriptions
        32. 7.7.1.32 GPIO3_CONFIG Register (Address = 0x1F) [reset = 0x2]
          1. Table 43. GPIO3_CONFIG Register Field Descriptions
        33. 7.7.1.33 GPIO5_6_CONFIG Register (Address = 0x20) [reset = 0x0]
          1. Table 44. GPIO5_6_CONFIG Register Field Descriptions
        34. 7.7.1.34 GPIO7_8_CONFIG Register (Address = 0x21) [reset = 0x0]
          1. Table 45. GPIO7_8_CONFIG Register Field Descriptions
        35. 7.7.1.35 DATAPATH_CONTROL Register (Address = 0x22) [reset = 0x0]
          1. Table 46. DATAPATH_CONTROL Register Field Descriptions
        36. 7.7.1.36 RX_MODE_STATUS Register (Address = 0x23) [reset = X]
          1. Table 47. RX_MODE_STATUS Register Field Descriptions
        37. 7.7.1.37 BIST_CONTROL Register (Address = 0x24) [reset = 0x8]
          1. Table 48. BIST_CONTROL Register Field Descriptions
        38. 7.7.1.38 BIST_ERROR_COUNT Register (Address = 0x25) [reset = 0x0]
          1. Table 49. BIST_ERROR_COUNT Register Field Descriptions
        39. 7.7.1.39 SCL_HIGH_TIME Register (Address = 0x26) [reset = 0x83]
          1. Table 50. SCL_HIGH_TIME Register Field Descriptions
        40. 7.7.1.40 SCL_LOW_TIME Register (Address = 0x27) [reset = 0x84]
          1. Table 51. SCL_LOW_TIME Register Field Descriptions
        41. 7.7.1.41 DATAPATH_CONTROL_2 Register (Address = 0x28) [reset = 0x20]
          1. Table 52. DATAPATH_CONTROL_2 Register Field Descriptions
        42. 7.7.1.42 FRC_CONTROL Register (Address = 0x29) [reset = 0x0]
          1. Table 53. FRC_CONTROL Register Field Descriptions
        43. 7.7.1.43 WHITE_BALANCE_CONTROL Register (Address = 0x2A) [reset = 0x0]
          1. Table 54. WHITE_BALANCE_CONTROL Register Field Descriptions
        44. 7.7.1.44 I2S_CONTROL Register (Address = 0x2B) [reset = 0x0]
          1. Table 55. I2S_CONTROL Register Field Descriptions
        45. 7.7.1.45 PCLK_TEST_MODE Register (Address = 0x2E) [reset = 0x0]
          1. Table 56. PCLK_TEST_MODE Register Field Descriptions
        46. 7.7.1.46 DUAL_RX_CTL Register (Address = 0x34) [reset = 0x1]
          1. Table 57. DUAL_RX_CTL Register Field Descriptions
        47. 7.7.1.47 AEQ_TEST Register (Address = 0x35) [reset = 0x0]
          1. Table 58. AEQ_TEST Register Field Descriptions
        48. 7.7.1.48 MODE_SEL Register (Address = 0x37) [reset = 0x0]
          1. Table 59. MODE_SEL Register Field Descriptions
        49. 7.7.1.49 I2S_DIVSEL Register (Address = 0x3A) [reset = 0x0]
          1. Table 60. I2S_DIVSEL Register Field Descriptions
        50. 7.7.1.50 EQ_STATUS Register (Address = 0x3B) [reset = 0x0]
          1. Table 61. EQ_STATUS Register Field Descriptions
        51. 7.7.1.51 LINK_ERROR_COUNT Register (Address = 0x41) [reset = 0x3]
          1. Table 62. LINK_ERROR_COUNT Register Field Descriptions
        52. 7.7.1.52 HSCC_CONTROL Register (Address = 0x43) [reset = 0x0]
          1. Table 63. HSCC_CONTROL Register Field Descriptions
        53. 7.7.1.53 ADAPTIVE_EQ_BYPASS Register (Address = 0x44) [reset = 0x60]
          1. Table 64. ADAPTIVE_EQ_BYPASS Register Field Descriptions
        54. 7.7.1.54 ADAPTIVE_EQ_MIN_MAX Register (Address = 0x45) [reset = 0x8]
          1. Table 65. ADAPTIVE_EQ_MIN_MAX Register Field Descriptions
        55. 7.7.1.55 FPD_TX_MODE Register (Address = 0x49) [reset = X]
          1. Table 66. FPD_TX_MODE Register Field Descriptions
        56. 7.7.1.56 LVDS_CONTROL Register (Address = 0x4B) [reset = 0x0]
          1. Table 67. LVDS_CONTROL Register Field Descriptions
        57. 7.7.1.57 CML_OUTPUT_CTL1 Register (Address = 0x52) [reset = 0x0]
          1. Table 68. CML_OUTPUT_CTL1 Register Field Descriptions
        58. 7.7.1.58 CML_OUTPUT_ENABLE Register (Address = 0x56) [reset = 0x0]
          1. Table 69. CML_OUTPUT_ENABLE Register Field Descriptions
        59. 7.7.1.59 CML_OUTPUT_CTL2 Register (Address = 0x57) [reset = 0x0]
          1. Table 70. CML_OUTPUT_CTL2 Register Field Descriptions
        60. 7.7.1.60 CML_OUTPUT_CTL3 Register (Address = 0x63) [reset = 0x0]
          1. Table 71. CML_OUTPUT_CTL3 Register Field Descriptions
        61. 7.7.1.61 PGCTL Register (Address = 0x64) [reset = 0x10]
          1. Table 72. PGCTL Register Field Descriptions
        62. 7.7.1.62 PGCFG Register (Address = 0x65) [reset = 0x0]
          1. Table 73. PGCFG Register Field Descriptions
        63. 7.7.1.63 PGIA Register (Address = 0x66) [reset = 0x0]
          1. Table 74. PGIA Register Field Descriptions
        64. 7.7.1.64 PGID Register (Address = 0x67) [reset = 0x0]
          1. Table 75. PGID Register Field Descriptions
        65. 7.7.1.65 PGDBG Register (Address = 0x68) [reset = 0x0]
          1. Table 76. PGDBG Register Field Descriptions
        66. 7.7.1.66 PGTSTDAT Register (Address = 0x69) [reset = 0x0]
          1. Table 77. PGTSTDAT Register Field Descriptions
        67. 7.7.1.67 GPI_PIN_STATUS_1 Register (Address = 0x6E) [reset = 0x0]
          1. Table 78. GPI_PIN_STATUS_1 Register Field Descriptions
        68. 7.7.1.68 GPI_PIN_STATUS_2 Register (Address = 0x6F) [reset = 0x0]
          1. Table 79. GPI_PIN_STATUS_2 Register Field Descriptions
        69. 7.7.1.69 RX_ID0 Register (Address = 0xF0) [reset = 0x5F]
          1. Table 80. RX_ID0 Register Field Descriptions
        70. 7.7.1.70 RX_ID1 Register (Address = 0xF1) [reset = 0x55]
          1. Table 81. RX_ID1 Register Field Descriptions
        71. 7.7.1.71 RX_ID2 Register (Address = 0xF2) [reset = 0x48]
          1. Table 82. RX_ID2 Register Field Descriptions
        72. 7.7.1.72 RX_ID3 Register (Address = 0xF3) [reset = 0x39]
          1. Table 83. RX_ID3 Register Field Descriptions
        73. 7.7.1.73 RX_ID4 Register (Address = 0xF4) [reset = 0x32]
          1. Table 84. RX_ID4 Register Field Descriptions
        74. 7.7.1.74 RX_ID5 Register (Address = 0xF5) [reset = 0x38]
          1. Table 85. RX_ID5 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from A Revision (January 2016) to B Revision

  • Changed PCLK frequency to support higher speed 192 MHz. Go
  • Changed "1.2 V" to "1.25 V" at top of DS90Ux940 Deserializer in Typ AppGo
  • Simplified the typical application by removing the power supplies nodes. Go
  • Removed bolded pin description name for power supplies. Go
  • Added new pin description content to the Pin Functions table Go
  • Changed the description from VDDIO to V(I2C). Go
  • Specified in current instead of resistor for all pulldown resistor Go
  • Removed 200-µA minimum ramp time for PDB pin description. Go
  • Added the description to clarify the INTB_IN that this pin can be an output driver.Go
  • Changed pin names from CAP_PLL0 and CAP_PLL1 to RES0 and RES1 respectively. Go
  • Removed tablenote from the Absolute Maximum Ratings table: For soldering specifications, see product folder at www.ti.com and SNOA549 Go
  • Added Military/Aerospace tablenote to the Absolute Maximum Ratings table Go
  • Changed supply voltage maximum for the VDD33 from: 4 V to: 3.96 V Go
  • Changed VDD12 abs max from 1.8V to 1.44V. Go
  • Changed supply voltage for the VDDIO from: 4 V to: 3.96 V Go
  • Added the Added the open-drain voltage, CML output voltage, and FPD-Link III input voltage parameters to the Absolute Maximum Ratings table , open-drain voltage, CML output voltage, and FPD-Link III input voltage parameters to the Absolute Maximum Ratings table Go
  • Added test conditions to the LVCMOS I/O voltage parameter Go
  • Spelled out all GPIOs pin name.Go
  • Combined the ESD ratings into one ESD Ratings table Go
  • Removed VDD18 test condition from the supply voltage parameter Go
  • Added the open-drain voltage parameter to the Recommended Operating Conditions table Go
  • Changed open LDI clock frequency (dual link) maximum from: 170 MHz to: 192 MHz Go
  • Added the local I2C frequency parameter to the Recommended Operating Conditions table Go
  • Added test conditions to the supply noise parameter Go
  • Changed the total power consumption, normal operation test conditions Go
  • Changed "VDD12 = 1.2 V" to "VDD12 = 1.2 V"Go
  • Removed the checkerboard vs. PRBS pattern condition and combined typical and worst case together. Go
  • Added current specs for PCLK 192 MHz. Go
  • Deleted typical value for Vih and Vil in 3.3V LVCMOS I/O.Go
  • Split out the test conditions in the 3.3-V and 1.8-V LVCMOS I/O parameters Go
  • Added strap pin input current parameter to the DC Electrical Characteristics table Go
  • Deleted typical value for Vih and Vil in 1.8V LVCMOS I/O. Go
  • Deleted typical value for Vih and Vil in serial control bus Go
  • Added test conditions to the input high level and input low level parameters Go
  • Changed "complimentary" to "complementary" Go
  • Removed tablenote from the AC Electrical Characteristics table: This parameter is specified by characterization and is not tested in production. Go
  • Changed differential output eye height from: >300 mV to: 300 mV Go
  • Removed tablenote from the Timing Requirements table: Parameter is specified by bench characterization and is not tested in production. Go
  • Changed Cb fast mode plus maximum value from: 550 pF to: 200 pF Go
  • Removed tablenote from the Switching Characteristics table: Parameter is specified by bench characterization and is not tested in production. Go
  • Changed Deserializer Eye Diagram graph in the Typical Characteristics sectionGo
  • Added paragraph explains HSCC mode.Go
  • Changed transmission distance section and insertion loss table. Go
  • Changed PCLK frequncy from 96 MHz to 192 MHz in the diagram "2-lane FPD-link Input, Link OpenLDI Output" in the Data-Path Configurations graphicGo
  • Changed the resistor ratio value for both the Configuration Select (MODE_SEL0) and Configuration Select (MODE_SEL1) tables.Go
  • Deleted repeated first paragraph LUT contents. Go
  • Changed pullup power supply node from "VDDIO" to "V(I2C). Go
  • Updated register table format to the latest TI standards in the Register Maps sectionGo
  • Changed input value from 1.2 V to 1.2 V in typical application drawings Go
  • Updated STP diagram. Go
  • Updated Coax diagramGo
  • Simplified the diagram by removing power supplies node. Go
  • Added new design parameters to the Design Requirements section Go
  • Changed VDD12 in Design Parameters 1.2 to 1.2 Go
  • Changed CML Interconnect Guidelines section title to FPD-Link III Interconnect Guidelines Go
  • Added AV Mute Prevention section Go
  • Added Prevention of I2C Errors During Abrupt System Faults section Go
  • Moved the Power Sequence graphic to the Power Supply RecommendationsGo
  • Removed power supplies columns and changed the parameters in the Power-Up Sequencing Constraints table according to the diagram. Go
  • Moved the PCB Layout and Power System Considerations content to the Layout Guidelines section Go
  • Added Ground and Routing FPD-Link III Signal Traces sections to the Layout sectionGo
  • Added Added FPD-Link training videos to the Related Documentation section. Go

Changes from * Revision (October 2014) to A Revision

  • Added shared pins description on SPI pins Go
  • Added shared pins description on GPIO pins Go
  • Added shared pins description on D_GPIO pins Go
  • Added shared pins description on register only GPIO pins. Changed "Local register control only" to "I2C register control only". Go
  • Added shared pins description on slave mode I2S pins Go
  • Added shared pins description on master mode I2S pins Go
  • Added legend for I/O TYPEGo
  • Moved Storage Temperature Range from ESD to Absolute Maximum Ratings table Go
  • Added ESD Ratings tableGo
  • Changed IDD12Z limit from 8mA to 30mA per PE re-characterization Go
  • Changed VOS from 1.0V to 1.125V Go
  • Changed VOS from 1.5V to 1.375V Go
  • Changed Fast Plus Mode tSP maximum from 20ns to 50ns Go
  • Added Image Enhancement Features section Go
  • Changed default value from "0" to "1" in register 0x01[2] Go
  • Added description to register 0x01[1] "Registers which are loaded by pin strap will be restored to their original strap value when this bit is set. These registers show ‘Strap’ as their default value in this table." Go
  • Added to 0x02[7] in Description column "A Digital reset 0x01[0] should be asserted after toggling Output Enable bit LOW to HIGH" Go
  • Added "Loaded from remote SER" in register 0x07[7:1] function columnGo
  • Changed signal detect bit to reserved Go
  • Changed from Reserved to Rev-ID in register 0x1D Function column Go
  • On register 0x22 added "(Loaded from remote SER)"Go
  • Corrected in register 0x24[3] 0: Bist configured through "bit 0" to "bits 2:0" in description Go
  • Added in register 0x24[2:1] additional descriptionGo
  • Changed in register 0x24[1] description to "internal" Go
  • Changed in register 0x24[2] description to "internal" Go
  • On register 0x28 added "Loaded from remote SER"Go
  • Added clarification description on register 0x37 MODE_SELGo
  • Merged on 0x45 bits[7:4\} and bits[3:0] default value: 0x08Go
  • Added Power Sequence section Go