10.3 Routing FPD-Link III Signal Traces
Routing the FPD-Link III signal traces between the RIN pins and the connector is the most critical pieces of a successful PCB layout. Figure 56 shows an example PCB layout. For additional PCB layout details of the example, refer to the DS90UH948-Q1EVM User's Guide (SNLU162).
The following list provides essential recommendations for routing the FPD-Link III signal traces between the receiver input pins (RIN) and the connector.
- The routing of the FPD-Link III traces may be all on the top layer or partially embedded in middle layers if EMI is a concern.
- The AC-coupling capacitors should be on the top layer and very close to the receiver input pins.
- Route the RIN traces between the AC-coupling capacitor and the connector as a 100-Ω differential micro-strip with tight impedance control (±10%). Calculate the proper width of the traces for a 100-Ω differential impedance based on the PCB stack-up.
- When choosing to implement a common mode choke for common mode noise reduction, minimize the effects of any impedance mismatch.
- Consult with connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impact of the thru-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side.