SNLS564B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHU|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-073D4B04-5AFA-4FC3-B668-8A0CE5F037E3-low.gif Figure 5-1 RHU Package, 56-Pin QFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CAPL 32 O Connect a single 2.2-µF capacitor to GND.
CTRL1 23 I/O

Host-side control interface. These pins are used to implement I2C or SPI depending on the PROTOCOL_SEL pin configuration.

I2C mode (PROTOCOL_SEL = Float or High):

CTRL1: SCL – I2C Clock input / open-drain output

CTRL2: SDA – I2C Data input / open-drain output

CTRL3: SET_ADDR_N – input, address assignment enable. Also used to receive external LED clock.

CTRL4: ADDR_DONE_N – output, address assignment complete. Also used to transmit LED clock.

SPI mode (PROTOCOL_SEL = GND):

CTRL1: SCK – Serial clock input

CTRL2: SS_N – Active-low slave select input

CTRL3: MOSI – Master output/ slave input

CTRL4: MISO – Master input / slave output
CTRL2 24 I/O
CTRL3 28 I, Weak internal pull-up
CTRL4 21 O
EN 22 VDD2 I, Weak internal pull-up Device enable. When EN=0, the FPC202 is in a power-down state and does not respond to the host-side control bus, nor does it perform port-side I2C accesses. When EN=VDD2 or Float, the FPC202 is fully enabled and will respond to the host-side control bus provided VDD1 and VDD2 power has been stable for at least TPOR. VIH for this pin is referenced to VDD2.

The minimum required assert and de-assert time is 12.5 µs.
GPIO[0] 42 VDD1 I/O General-purpose I/O. Output high voltage (VOH) and input high voltage (VIH) are based on VDD1. Configured as input (high-Z) by default.
GPIO[1] 53
GPIO[2] 8
GPIO[3] 19
GND 27, DAP Power Ground reference. The GND pins should be connected through a low-resistance path to the board GND plane.
HOST_INT_N 25 VDD1/VDD2 O, Open-Drain Open-drain 3.3-V tolerant active-low interrupt output. It asserts low to interrupt the host. The events which trigger an interrupt are programmable through registers. This pin can be connected in a wired-OR fashion with other FPC202s’ interrupt pins. A single pull-up resistor to VDD1 or VDD2 in the 2-kΩ to 5-kΩ range is adequate for the entire net.
P0_S0_IN_A 41 I, Weak internal pull-up

Low-speed port status input A.

Example usage:

SFP: Mod_ABS[1:0]

QSFP: ModPrsL[1:0]
P1_S0_IN_A 55
P0_S0_IN_B 39 I, Weak internal pull-up

Low-speed port status input B.

Example usage:

SFP: Tx_Fault[1:0]

QSFP: IntL[1:0]
P1_S0_IN_B 1
P0_S0_IN_C 37 I, Weak internal pull-up

Low-speed port status input C.

Example usage:

SFP: Rx_LOS[1:0]

QSFP: N/A
P1_S0_IN_C 3
P0_S1_IN_A 50 VDD1 I, Weak internal pull-up General-purpose inputs. Input high voltage (VIH) is based on VDD1.
P1_S1_IN_A 10
P0_S1_IN_B 47
P1_S1_IN_B 12
P0_S1_IN_C 46
P1_S1_IN_C 14
P0_MOD_SCL 36 I/O, Open-Drain I2C clock open-drain output to the module. External 2-kΩ to 5-kΩ pull-up resistor is required. This pin is 3.3-V LVCMOS tolerant.
P1_MOD_SCL 4
P0_MOD_SDA 35 I/O, Open-Drain I2C data input / open-drain output to the module. External 2-kΩ to 5-kΩ pull-up resistor is required. This pin is 3.3-V LVCMOS tolerant.
P1_MOD_SDA 5
RSV1 49 I/O Reserved. Must be left as no connect.
RSV2 15
RSV3 48
RSV4 16
P0_S0_OUT_A 40 O

Low-speed port control output A. OUT_A is disabled by default (high-Z) and when enabled drives high logic unless reprogrammed. A 10-kΩ pull-up or pull-down resistor is recommended to set a default logic value before this output is enabled. See Section 7.3.3 for more details.

Example usage:

SFP: Tx_Disable[1:0]

QSFP: ResetL[1:0]
P1_S0_OUT_A 56
P0_S0_OUT_B 38 O

Low-speed port control output B. Output is disabled by default (high-Z) and when enabled drives low logic unless reprogrammed. A 10-kΩ pull-up or pull-down resistor is recommended to set a default logic value before this output is enabled. See Section 7.3.3 for more details.

Example usage:

SFP: RS[1:0]

QSFP: LPMode[1:0]
P1_S0_OUT_B 2
P0_S0_OUT_C 34 O

General-purpose outputs with special LED driving features for automatic blinking and dimming. Can be used to drive port status LED. This output is enabled and high logic by default at power-up. See Section 7.3.2 for more details.

This pin requires a series resistor with a value of at least 33 Ω when driving an LED.
P1_S0_OUT_C 6
P0_S0_OUT_D 33
P1_S0_OUT_D 7
P0_S1_OUT_A 44 VDD1 O General-purpose outputs. Output high voltage (VOH) is based on VDD1.
P1_S1_OUT_A 11
P0_S1_OUT_B 45
P1_S1_OUT_B 13
P0_S1_OUT_C 51 O

General-purpose outputs with special LED driving features for automatic blinking and dimming. Can be used to drive port status LED. This output is enabled and high logic by default at power-up. See Section 7.3.2 for more details.

This pin requires a series resistor with a value of at least 33 Ω when driving an LED.
P1_S1_OUT_C 17
P0_S1_OUT_D 52
P1_S1_OUT_D 18
PROTOCOL_SEL 31 I, Weak internal pull-up Used to select between I2C and SPI host-side control interface.
Float or High: Inter-IC Control (I2C)
GND: Serial Peripheral Interface (SPI)
SPI_LED_SYNC 30 I/O

LED clock synchronization pin for SPI mode only.

When using SPI as the host-side control interface (PROTOCOL_SEL=GND), connect all FPC202 SPI_LED_SYNC pins together. This ensures LED synchronization across all FPC202 devices.

When using I2C as the host-side control interface, this pin can be floating. LED synchronization is ensured by other means in I2C mode.
TEST_N 29 I, Weak internal pull-up TI test mode.
Float or High: Normal operation
GND: TI Test Mode
VDD1 9, 43, 54 Power Main power supply, VDD1 = 3.3 V ± 5%. TI recommends connecting at least one 1-µF and one 0.1-µF de-coupling capacitors per VDD1 pin as close to the pin as possible.
VDD2 20, 26 Power Power supply for host-side interface I/Os (CTRL[4:1]). VDD2 can be 1.8 V to 3.3 V ± 5%. If the host-side interface operates at 3.3 V, then VDD1 and VDD2 can be connected to the same 3.3-V ± 5% supply. TI recommends connecting at least one 1-µF and one 0.1-µF de-coupling capacitors per VDD2 pin as close to the pin as possible.
(1) I = Input, O = Output