SLYS017D April   2018  – July 2022 INA180-Q1 , INA2180-Q1 , INA4180-Q1

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 High Bandwidth and Slew Rate
      2. 8.3.2 Wide Input Common-Mode Voltage Range
      3. 8.3.3 Precise Low-Side Current Sensing
      4. 8.3.4 Rail-to-Rail Output Swing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Input Differential Overload
      3. 8.4.3 Shutdown Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 RSENSE and Device Gain Selection
      3. 9.1.3 Signal Filtering
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Common-Mode Transients Greater Than 26 V
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Filtering

Provided that the INAx180-Q1 output is connected to a high impedance input, the best location to filter is at the device output using a simple RC network from OUT to GND. Filtering at the output attenuates high-frequency disturbances in the common-mode voltage, differential input signal, and INAx180-Q1 power-supply voltage. If filtering at the output is not possible, or filtering of only the differential input signal is required, it is possible to apply a filter at the input pins of the device. Figure 9-2 provides an example of how a filter can be used on the input pins of the device.

GUID-1F350F79-7327-4C30-94E5-3B673090ED40-low.gifFigure 9-2 Filter at Input Pins

The addition of external series resistance creates an additional error in the measurement; therefore, the value of these series resistors must be kept to 10 Ω (or less, if possible) to reduce impact to accuracy. The internal bias network shown in Figure 9-2 present at the input pins creates a mismatch in input bias currents when a differential voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch creates a differential error voltage that subtracts from the voltage developed across the shunt resistor. This error results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor. Without the additional series resistance, the mismatch in input bias currents has little effect on device operation. The amount of error these external filter resistors add to the measurement can be calculated using Equation 5, where the gain error factor is calculated using Equation 4.

The amount of variance in the differential voltage present at the device input relative to the voltage developed at the shunt resistor is based both on the external series resistance (RF) value as well as internal input resistor RINT, as shown in Figure 9-2. The reduction of the shunt voltage reaching the device input pins appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A factor can be calculated to determine the amount of gain error that is introduced by the addition of external series resistance. Calculate the expected deviation from the shunt voltage to what is measured at the device input pins is given using Equation 4:

Equation 4. GUID-02EDAFF0-5EBF-42F9-AF53-43F04995DA7F-low.gif

where:

  • RINT is the internal input resistor.
  • RF is the external series resistance.

With the adjustment factor from Equation 4, including the device internal input resistance, this factor varies with each gain version, as shown in Table 9-1. Each individual device gain error factor is shown in Table 9-2.

Table 9-1 Input Resistance
PRODUCTGAINRINT (kΩ)
INAx180A1-Q12025
INAx180A2-Q15010
INAx180A3-Q11005
INAx180A4-Q12002.5
Table 9-2 Device Gain Error Factor
PRODUCTSIMPLIFIED GAIN ERROR FACTOR
INAx180A1-Q1 GUID-5FB9BEA7-5362-4A1F-9880-B0821968EF3F-low.gif
INAx180A2-Q1 GUID-C26D6702-7976-4CC6-B60C-9D1099C70E3E-low.gif
INAx180A3-Q1 GUID-2C53EE09-39AE-4AFA-AB7B-F0FA850EF2B9-low.gif
INAx180A4-Q1 GUID-221BB02F-1E29-4487-81FF-F2149A9261F6-low.gif

The gain error that can be expected from the addition of the external series resistors can then be calculated based on Equation 5:


Equation 5. GUID-0A092707-4731-4945-B32C-94C91EBFA501-low.gif

For example, using an INA180A2-Q1 and the corresponding gain error equation from Table 9-2, a series resistance of
10 Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using Equation 5, resulting in an additional gain error of approximately 0.89% solely because of the external 10-Ω series resistors.