SNOSDI7 December   2023 LDC5071-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Diagnostics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Supply Voltage
      2. 6.3.2 Excitation Signal
      3. 6.3.3 Signal Processing Block
        1. 6.3.3.1 Demodulation
        2. 6.3.3.2 Fixed Gain Control
        3. 6.3.3.3 Automatic Gain Control
      4. 6.3.4 Output Stage
      5. 6.3.5 Diagnostics
        1. 6.3.5.1 Undervoltage Diagnostics
        2. 6.3.5.2 Initialization Diagnostics
        3. 6.3.5.3 Normal State Diagnostics
        4. 6.3.5.4 Fault State Diagnostics
    4. 6.4 Device Functional Modes
      1. 6.4.1 IDLE State
      2. 6.4.2 DIAGNOSTICS State
      3. 6.4.3 NORMAL State
      4. 6.4.4 FAULT State
      5. 6.4.5 DISABLED State
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 5-V Supply Mode
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 VREG and VCC
          2. 7.2.1.2.2 Output Capacitors
          3. 7.2.1.2.3 Automatic Gain Control (AGC) Mode
        3. 7.2.1.3 Application Curve
      2. 7.2.2 3.3-V Supply Mode
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 VREG and VCC
          2. 7.2.2.2.2 Output Capacitors
          3. 7.2.2.2.3 Fixed Gain Mode
      3. 7.2.3 Redundancy Mode
      4. 7.2.4 Single-Ended Mode
      5. 7.2.5 External Diagnostics Required for Loss of VCC or GND
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Mode 1: VCC = 5 V, VREG = 3.3 V
      2. 7.3.2 Mode 2: VCC = VREG = 3.3 V
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5.3 Normal State Diagnostics

During normal device operation, a number of parameters are continuously monitored

For the following parameters, if a fault condition is detected, the device is transferred to the FAULT state. Only if the fault condition is cleared then the part transitions to DIAGNOSTIC state (for fault thresholds refer to Diagnostics and for deglitch times refer to Switching Characteristics):

  • VREG overvoltage check: if the VREG voltage exceeds the VOVUTH_VREG, fault condition is detected in the tVREG_OV_DT. This fault detection delay allows the LDC5071-Q1 to filter out short glitches on the VREG pin. After the voltage drops below the VOVLTH_VREG, the fault condition is cleared.

For the following parameters, if a fault condition is detected, the device is transferred to the FAULT state and then to the DIAGNOSTICS state to attempt recovery and detect if the fault is still present. The zero-crossing mentioned in this section refers to crossing of the common voltage of a differential signal pair.

  • Output signal voltage check: this diagnostic compares the states of the zero-crossing comparators of OUT pins with the corresponding zero-crossing comparators of the AGC block outputs. A valid rotational signal must be present for this check, and the detection time, will depend on the rotational speed of the motor.

For the following parameters, if a fault condition is detected, the device is transferred to the DISABLED state and a recovery is attempted (see DISABLED State):

  • Register CRC check: the LDC5071-Q1 calculates the CRC value of the safety-critical register settings and compares the CRC value to the recorded expected CRC value. In case of FAULT, the LDC5071-Q1 transitions to the DISABLED state. This check is performed continuously.
  • Critical registers redundancy check: the device checks the validity of the critical registers versus its redundant copy. In case of a discrepancy, the device immediately transitions to the DISABLED state
  • TM0 state check: the device checks if the TM0 pin state was changed after its state was determined during Initialization diagnostics.
  • TOUT state check: the device checks if the TOUT pin state was changed after its state was determined during Initialization diagnostics.
  • AGC_EN toggle check: the device checks if the AGC_EN state was changed after its state was determined during Initialization diagnostics. This check has a deglitch time of tAGC_EN_TGL_DT